Fix a typo in StarFive JH7110 pin function definitions for GPOUT_SYS_SDIO1_DATA4

Fixes: e22f09e598d12 ("riscv: dts: starfive: Add StarFive JH7110 pin function definitions")
Signed-off-by: E Shattow <e@freeshell.de>
Acked-by: Hal Feng <hal.feng@starfivetech.com>
CC: stable@vger.kernel.org
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Pull RISC-V updates from Palmer Dabbelt:

 - The PH1520 pinctrl and dwmac drivers are enabeled in defconfig

 - A redundant AQRL barrier has been removed from the futex cmpxchg
   implementation

 - Support for the T-Head vector extensions, which includes exposing
   these extensions to userspace on systems that implement them

 - Some more page table information is now printed on die() and systems
   that cause PA overflows

* tag 'riscv-for-linus-6.14-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: add a warning when physical memory address overflows
  riscv/mm/fault: add show_pte() before die()
  riscv: Add ghostwrite vulnerability
  selftests: riscv: Support xtheadvector in vector tests
  selftests: riscv: Fix vector tests
  riscv: hwprobe: Document thead vendor extensions and xtheadvector extension
  riscv: hwprobe: Add thead vendor extension probing
  riscv: vector: Support xtheadvector save/restore
  riscv: Add xtheadvector instruction definitions
  riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT
  RISC-V: define the elements of the VCSR vector CSR
  riscv: vector: Use vlenb from DT for thead
  riscv: Add thead and xtheadvector as a vendor extension
  riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree
  dt-bindings: cpus: add a thead vlen register length property
  dt-bindings: riscv: Add xtheadvector ISA extension description
  RISC-V: Mark riscv_v_init() as __init
  riscv: defconfig: drop RT_GROUP_SCHED=y
  riscv/futex: Optimize atomic cmpxchg
  riscv: defconfig: enable pinctrl and dwmac support for TH1520

Pull SoC devicetree updates from Arnd Bergmann:
 "We see the addition of eleven new SoCs, including a total of sixx
  arm64 chips from Qualcomm alone. Overall, the Qualcomm platforms once
  again make up the majority of all changes, after a couple of quieter
  releases.

  The new SoCs in this branch are:

   - Microchip sama7d65 is a new 32-bit embedded chip with a single
     Cortex-A7 and the current high end of the old Atmel SoC line.

   - Samsung Exynos 9810 is a mobile phone chip used in some older
     phones like the Samsung Galaxy S9

   - Renesas R-Car V4H ES3.0 (R8A779G3) is an updated version of the V4H
     (R8A779G0) low-power automotive SoC

   - Renesas RZ/G3E (R0A09G047) is a family of embedded chips using
     Cortex-A55 cores

   - Qualcomm Snapdragon 8 Elite (SM8750) is a new phone chip based on
     Qualcomm's Oryon CPU cores.

   - Qualcomm Snapdragon AR2 (SAR2130P) is a SoC for augmented reality
     glasses.

   - Qualcomm IQ6 (QCS610) and IQ8 (QCS8300) are two industrial IOT
     platforms.

   - Snapdragon 425 (MSM8917) is a mobile phone SoC from 2016

   - Qualcomm IPQ5424 is a Wi-Fi 7 networking chip

  All of the above are part of already supported SoC families that only
  need new devicetree files. Two additional SoCs in new families are
  part of a separate branch.

  There are 48 new machines in total, including six arm32 ones based on
  aspeed. broadcom, microchip and st SoCs all using Cortex-A7 cores, and
  a single risc-v board, the Banana Pi R3.

  The remaining ones use arm64 chips from Broadcom, Samsung, NXP,
  Mediatek, Qualcomm, Renesas and Rockchips and cover development
  boards, phones, laptops, industrial machines routers.

 A lot of ongoing work is for cleaning up build time warnings and other
 issues, in addition to the new machines and added features"

* tag 'soc-dt-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (619 commits)
  arm64: tegra: Fix Tegra234 PCIe interrupt-map
  arm64: dts: qcom: x1e80100-romulus: Update firmware nodes
  arm64: dts: rockchip: add DTs for Firefly ITX-3588J and its Core-3588J SoM
  dt-bindings: arm: rockchip: Add Firefly ITX-3588J board
  arm64: dts: rockchip: Add Orange Pi 5 Max board
  dt-bindings: arm: rockchip: Add Xunlong Orange Pi 5 Max
  arm64: dts: rockchip: refactor common rk3588-orangepi-5.dtsi
  arm64: dts: rockchip: add WLAN to rk3588-evb1 controller
  arm64: dts: rockchip: increase gmac rx_delay on rk3399-puma
  arm64: dts: rockchip: Delete redundant RK3328 GMAC stability fixes
  arm64: tegra: Disable Tegra234 sce-fabric node
  arm64: tegra: Fix typo in Tegra234 dce-fabric compatible
  arm64: tegra: Fix DMA ID for SPI2
  arm64: dts: qcom: msm8916-samsung-serranove: Add display panel
  arm64: dts: qcom: sm8650: Add 'global' interrupt to the PCIe RC nodes
  arm64: dts: qcom: sm8550: Add 'global' interrupt to the PCIe RC nodes
  arm64: dts: qcom: Remove unused and undocumented properties
  arm64: dts: qcom: sdm450-lenovo-tbx605f: add DSI panel nodes
  arm64: dts: qcom: pmi8950: add LAB-IBB nodes
  arm64: dts: qcom: ipq5424: enable the download mode support
  ...

Charlie Jenkins <charlie@rivosinc.com> says:

xtheadvector is a custom extension that is based upon riscv vector
version 0.7.1 [1]. All of the vector routines have been modified to
support this alternative vector version based upon whether xtheadvector
was determined to be supported at boot.

vlenb is not supported on the existing xtheadvector hardware, so a
devicetree property thead,vlenb is added to provide the vlenb to Linux.

There is a new hwprobe key RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 that is
used to request which thead vendor extensions are supported on the
current platform. This allows future vendors to allocate hwprobe keys
for their vendor.

Support for xtheadvector is also added to the vector kselftests.

[1] https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc

* b4-shazam-merge:
  riscv: Add ghostwrite vulnerability
  selftests: riscv: Support xtheadvector in vector tests
  selftests: riscv: Fix vector tests
  riscv: hwprobe: Document thead vendor extensions and xtheadvector extension
  riscv: hwprobe: Add thead vendor extension probing
  riscv: vector: Support xtheadvector save/restore
  riscv: Add xtheadvector instruction definitions
  riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT
  RISC-V: define the elements of the VCSR vector CSR
  riscv: vector: Use vlenb from DT for thead
  riscv: Add thead and xtheadvector as a vendor extension
  riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree
  dt-bindings: cpus: add a thead vlen register length property
  dt-bindings: riscv: Add xtheadvector ISA extension description

Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-0-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

The D1/D1s SoCs support xtheadvector so it can be included in the
devicetree. Also include vlenb for the cpu.

Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-3-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

aliases info should belong to board dts, instead of
putting it at SoC dtsi file.

Fixes: d8fe64691955 ("riscv: dts: add initial SpacemiT K1 SoC device tree")
Link: https://lore.kernel.org/all/6a8bb914-858e-479d-a7d9-09e0ff688160@app.fastmail.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>

Before pinctrl driver implemented, the uart0 controller reply on
bootloader for setting correct pin mux and configurations.

Now, let's add pinctrl property to uart0 of Bananapi-F3 board.

Signed-off-by: Yixun Lan <dlan@gentoo.org>

Banana Pi BPI-F3 [1] is a industrial grade RISC-V development board, it
design with SpacemiT K1 8 core RISC-V chip [2].

Currently only support booting into console with only uart enabled,
other features will be added soon later.

Link: https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3 [1]
Link: https://www.spacemit.com/en/spacemit-key-stone-2/ [2]
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Jesse Taube <jesse@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>

Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].

Key features:
- 4 cores per cluster, 2 clusters on chip
- UART IP is Intel XScale UART

Some key considerations:
- ISA string is inferred from vendor documentation[2]
- Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
- No coherent DMA on this board
    Inferred by taking vendor ethernet and MMC drivers to the mainline
    kernel. Without dma-noncoherent in soc node, the driver fails.
- Add cache nodes
    K1 SoC has 128 sets of 32KiB L1 I/D Cache for each hart, and 512 sets
    of 512KiB L2 Cache for each cluster.

Currently only support booting into console with only uart, other
features will be added soon later.

Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Jesse Taube <jesse@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>

~RISC-V~ StarFive Devicetrees for v6.14

Not so much RISC-V, but rather StarFive, this time around as there are
only two changes: the Milk-V Mars and Pine64 Star64 boards get their usb0
interfaces moved from peripheral to host mode.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: starfive: jh7110-milkv-mars: enable usb0 host function
  riscv: dts: starfive: jh7110-pine64-star64: enable usb0 host function

Link: https://lore.kernel.org/r/20250113-kennel-outplayed-21a52a654c36@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>