linux.git/arch/riscv/boot, branch v5.15

riscv: dts: microchip: mpfs-icicle: Fix serial console

2021-09-11T06:58:19+00:00

Currently, nothing is output on the serial console, unless
"console=ttyS0,115200n8" or "earlycon" are appended to the kernel
command line.  Enable automatic console selection using
chosen/stdout-path by adding a proper alias, and configure the expected
serial rate.

While at it, add aliases for the other three serial ports, which are
provided on the same micro-USB connector as the first one.

Fixes: 0fa6107eca4186ad ("RISC-V: Initial DTS for Microchip ICICLE board")
Signed-off-by: Geert Uytterhoeven 
Reviewed-by: Bin Meng 
Reviewed-by: Conor Dooley 
Signed-off-by: Palmer Dabbelt

riscv: move the (z)install rules to arch/riscv/Makefile

2021-09-11T06:08:26+00:00

Currently, the (z)install targets in arch/riscv/Makefile descend into
arch/riscv/boot/Makefile to invoke the shell script, but there is no
good reason to do so.

arch/riscv/Makefile can run the shell script directly.

Signed-off-by: Masahiro Yamada 
Signed-off-by: Palmer Dabbelt

riscv: dts: microchip: Add ethernet0 to the aliases node

2021-08-25T03:57:32+00:00

U-Boot expects this alias to be in place in order to fix up the mac
address of the ethernet node.

Note on the Icicle Kit board, currently only emac1 is enabled so it
becomes the 'ethernet0'.

Signed-off-by: Bin Meng 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Palmer Dabbelt

riscv: dts: microchip: Use 'local-mac-address' for emac1

2021-08-25T03:56:47+00:00

Per the DT spec, 'local-mac-address' is used to specify MAC address
that was assigned to the network device, while 'mac-address' is used
to specify the MAC address that was last used by the boot program,
and shall be used only if the value differs from 'local-mac-address'
property value.

Signed-off-by: Bin Meng 
Reviewed-by: conor dooley 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Palmer Dabbelt

riscv: dts: fix memory size for the SiFive HiFive Unmatched

2021-08-04T04:15:31+00:00

The production version of HiFive Unmatched have 16GB memory.

Signed-off-by: Qiu Wenbo 
Signed-off-by: Palmer Dabbelt

riscv: dts: fu740: fix cache-controller interrupts

2021-06-19T07:11:53+00:00

The order of interrupt numbers is incorrect.

The order for FU740 is: DirError, DataError, DataFail, DirFail

From SiFive FU740-C000 Manual:
19 - L2 Cache DirError
20 - L2 Cache DirFail
21 - L2 Cache DataError
22 - L2 Cache DataFail

Signed-off-by: David Abdurachmanov 
Signed-off-by: Palmer Dabbelt

riscv: Fix BUILTIN_DTB for sifive and microchip soc

2021-06-12T04:07:09+00:00

Fix BUILTIN_DTB config which resulted in a dtb that was actually not
built into the Linux image: in the same manner as Canaan soc does,
create an object file from the dtb file that will get linked into the
Linux image.

Signed-off-by: Alexandre Ghiti 
Signed-off-by: Palmer Dabbelt

Merge tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

2021-05-06T16:24:18+00:00

Pull RISC-V updates from Palmer Dabbelt:

- Support for the memtest= kernel command-line argument.

- Support for building the kernel with FORTIFY_SOURCE.

- Support for generic clockevent broadcasts.

- Support for the buildtar build target.

- Some build system cleanups to pass more LLVM-friendly arguments.

- Support for kprobes.

- A rearranged kernel memory map, the first part of supporting sv48
systems.

- Improvements to kexec, along with support for kdump and crash
kernels.

- An alternatives-based errata framework, along with support for
handling a pair of errata that manifest on some SiFive designs
(including the HiFive Unmatched).

- Support for XIP.

- A device tree for the Microchip PolarFire ICICLE SoC and associated
dev board.

... along with a bunch of cleanups. There are already a handful of fixes
on the list so there will likely be a part 2.

* tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (45 commits)
RISC-V: Always define XIP_FIXUP
riscv: Remove 32b kernel mapping from page table dump
riscv: Fix 32b kernel build with CONFIG_DEBUG_VIRTUAL=y
RISC-V: Fix error code returned by riscv_hartid_to_cpuid()
RISC-V: Enable Microchip PolarFire ICICLE SoC
RISC-V: Initial DTS for Microchip ICICLE board
dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC
RISC-V: Add Microchip PolarFire SoC kconfig option
RISC-V: enable XIP
RISC-V: Add crash kernel support
RISC-V: Add kdump support
RISC-V: Improve init_resources()
RISC-V: Add kexec support
RISC-V: Add EM_RISCV to kexec UAPI header
riscv: vdso: fix and clean-up Makefile
riscv/mm: Use BUG_ON instead of if condition followed by BUG.
riscv/kprobe: fix kernel panic when invoking sys_read traced by kprobe
riscv: Set ARCH_HAS_STRICT_MODULE_RWX if MMU
riscv: module: Create module allocations without exec permissions
riscv: bpf: Avoid breaking W^X
...

riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC

2021-05-04T13:58:32+00:00

Link: https://lore.kernel.org/r/20210504105940.100004-7-greentime.hu@sifive.com
Signed-off-by: Greentime Hu 
Signed-off-by: Lorenzo Pieralisi 
Acked-by: Palmer Dabbelt

RISC-V: Initial DTS for Microchip ICICLE board

2021-04-26T15:31:31+00:00

Add initial DTS for Microchip ICICLE board having only
essential devices (clocks, sdhci, ethernet, serial, etc).
The device tree is based on the U-Boot patch.

https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/

Signed-off-by: Atish Patra 
Signed-off-by: Palmer Dabbelt