linux.git/arch/ppc64/kernel/Makefile, branch v2.6.14

[PATCH] ppc64: Split SCC and 15550 udbg code

2005-09-06T06:07:36+00:00

Split scc and 15550 functions from udbg each into their own file.
This makes them more symetric with the lpar and btext code.

Signed-off-by: Milton Miller 
Signed-off-by: Anton Blanchard 
Signed-off-by: Paul Mackerras

[PATCH] ppc64: make firmware_has_feature() stronger

2005-08-29T00:53:35+00:00

Make firmware_has_feature() evaluate at compile time for the non pSeries
case and tidy up code where possible.

Signed-off-by: Stephen Rothwell 
Signed-off-by: Paul Mackerras

[PATCH] ppc64: split pSeries specific parts out of vio.c

2005-08-29T00:53:32+00:00

This patch just splits out the pSeries specific parts of vio.c.

Signed-off-by: Stephen Rothwell 
Signed-off-by: Paul Mackerras

[PATCH] ppc64: split iSeries specific parts out of vio.c

2005-08-29T00:53:32+00:00

This patch splits the iSeries specific parts out of vio.c.

Signed-off-by: Stephen Rothwell 
Signed-off-by: Paul Mackerras

[PATCH] iSeries build with newer assemblers and compilers

2005-08-17T04:06:25+00:00

Paulus suggested that we put xLparMap in its own .c file so that we can
generate a .s file to be included into head.S.  This doesn't get around
the problem of having it at a fixed address, but it makes it more
palatable.

It would be good if this could be included in 2.6.13 as it solves our
build problems with various versions of binutils and gcc.  In
particular, it allows us to build an iSeries kernel on Debian unstable
using their biarch compiler.

This has been built and booted on iSeries and built for pSeries and g5.

Signed-off-by: Stephen Rothwell 
Signed-off-by: Paul Mackerras 
Signed-off-by: Linus Torvalds

[PATCH] ppc64: kexec support for ppc64

2005-06-25T23:24:51+00:00

This patch implements the kexec support for ppc64 platforms.

A couple of notes:

1)  We copy the pages in virtual mode, using the full base kernel
    and a statically allocated stack.   At kexec_prepare time we
    scan the pages and if any overlap our (0, _end[]) range we
    return -ETXTBSY.

    On PowerPC 64 systems running in LPAR (logical partitioning)
    mode, only a small region of memory, referred to as the RMO,
    can be accessed in real mode.  Since Linux runs with only one
    zone of memory in the memory allocator, and it can be orders of
    magnitude more memory than the RMO, looping until we allocate
    pages in the source region is not feasible.  Copying in virtual
    means we don't have to write a hash table generation and call
    hypervisor to insert translations, instead we rely on the pinned
    kernel linear mapping.  The kernel already has move to linked
    location built in, so there is no requirement to load it at 0.

    If we want to load something other than a kernel, then a stub
    can be written to copy a linear chunk in real mode.

2)  The start entry point gets passed parameters from the kernel.
    Slaves are started at a fixed address after copying code from
    the entry point.

    All CPUs get passed their firmware assigned physical id in r3
    (most calling conventions use this register for the first
    argument).

    This is used to distinguish each CPU from all other CPUs.
    Since firmware is not around, there is no other way to obtain
    this information other than to pass it somewhere.

    A single CPU, referred to here as the master and the one executing
    the kexec call, branches to start with the address of start in r4.
    While this can be calculated, we have to load it through a gpr to
    branch to this point so defining the register this is contained
    in is free.  A stack of unspecified size is available at r1
    (also common calling convention).

    All remaining running CPUs are sent to start at absolute address
    0x60 after copying the first 0x100 bytes from start to address 0.
    This convention was chosen because it matches what the kernel
    has been doing itself.  (only gpr3 is defined).

    Note: This is not quite the convention of the kexec bootblock v2
    in the kernel.  A stub has been written to convert between them,
    and we may adjust the kernel in the future to allow this directly
    without any stub.

3)  Destination pages can be placed anywhere, even where they
    would not be accessible in real mode.  This will allow us to
    place ram disks above the RMO if we choose.

Signed-off-by: Milton Miller 
Signed-off-by: R Sharada 
Signed-off-by: Paul Mackerras 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

[PATCH] ppc64: Add driver for BPA iommu

2005-06-22T23:43:54+00:00

Implementation of software load support for the BE iommu. This is very
different from other iommu code on ppc64, since we only do a static mapping.
The mapping is currently hardcoded but should really be read from the
firmware, but they don't set up the device nodes yet. There is a single
512MB DMA window for PCI, USB and ethernet at 0x20000000 for our RAM.

The Cell processor can put the I/O page table either in memory like
the hashed page table (hardware load) or have the operating system
write the entries into memory mapped CPU registers (software load).

I use the software load mechanism because I know that all I/O page
table entries for the amount of installed physical memory fit into
the IO TLB cache. At the point when we get machines with more than
4GB of installed memory, we can either use hardware I/O page table
access like the other platforms do or dynamically update the I/O
TLB entries when a page fault occurs in the I/O subsystem.

The software load can then use the macros that I have implemented
for the static mapping in order to do the TLB cache updates.

Signed-off-by: Arnd Bergmann 
Signed-off-by: Paul Mackerras

[PATCH] ppc64: Add driver for BPA interrupt controllers

2005-06-22T23:43:43+00:00

Add support for the integrated interrupt controller on BPA
CPUs. There is one of those for each SMT thread.

The mapping of interrupt numbers to HW interrupt sources
is described in arch/ppc64/kernel/bpa_iic.h.

This version hardcodes the 'Spider' chip as the secondary
interrupt controller. That is not really generic for the
architecture, but at the moment it is the only secondary
PIC that exists.

A little more work will be needed on this as soon as
we have boards with multiple external interrupt controllers.

Signed-off-by: Arnd Bergmann 
Signed-off-by: Paul Mackerras

[PATCH] ppc64: add BPA platform type

2005-06-22T23:43:37+00:00

This adds the basic support for running on BPA machines.
So far, this is only the IBM workstation, and it will
not run on others without a little more generalization.

It should be possible to configure a kernel for any
combination of CONFIG_PPC_BPA with any of the other
multiplatform targets.

Signed-off-by: Arnd Bergmann 
Signed-off-by: Paul Mackerras

[PATCH] ppc64: Split out generic rtas code from pSeries_pci.c.

2005-06-22T23:43:23+00:00

BPA is using rtas for PCI but should not be confused by
pSeries code. This also avoids some #ifdefs. Other
platforms that want to use rtas_pci.c could create
their own platform_pci.c with platform specific fixups.

Signed-off-by: Arnd Bergmann 
Signed-off-by: Paul Mackerras