linux.git/arch/powerpc/sysdev/mpic.c, branch v2.6.24

Add dcr_host_t.base in dcr_read()/dcr_write()

2007-10-15T18:29:49+00:00

Now that all users of dcr_read()/dcr_write() add the dcr_host_t.base, we
can save them the trouble and do it in dcr_read()/dcr_write().

As some background to why we just went through all this jiggery-pokery,
benh sayeth:

 Initially the goal of the dcr_read/dcr_write routines was to operate like
 mfdcr/mtdcr which take absolute DCR numbers. The reason is that on 4xx
 hardware, indirect DCR access is a pain (goes through a table of
 instructions) and it's useful to have the compiler resolve an absolute DCR
 inline.

 We decided that wasn't worth the API bastardisation since most places
 where absolute DCR values are used are low level 4xx-only code which may
 as well continue using mfdcr/mtdcr, while the new API is designed for
 device "instances" that can exist on 4xx and Axon type platforms and may
 be located at variable DCR offsets.

Signed-off-by: Michael Ellerman 
Signed-off-by: Jeff Garzik

[POWERPC] Update mpic to use dcr_host_t.base

2007-10-03T03:25:27+00:00

Now that dcr_host_t contains the base address, we can use that in the mpic
code, rather than storing it separately.

Signed-off-by: Michael Ellerman 
Acked-by: Benjamin Herrenschmidt 
Signed-off-by: Paul Mackerras

[POWERPC] Support setting affinity for U3/U4 MSI sources

2007-09-22T04:49:22+00:00

Hook up affinity-setting for U3/U4 MSI interrupt sources.

Tested on Quad G5 with myri10ge.

Signed-off-by: Olof Johansson 
Acked-by: Benjamin Herrenschmidt 
Acked-by: Michael Ellerman 
Signed-off-by: Paul Mackerras

[POWERPC] Add workaround for MPICs with broken register reads

2007-09-13T15:33:25+00:00

Some versions of PWRficient 1682M have an interrupt controller in which
the first register in each pair for interrupt sources doesn't always
read with the right polarity/sense values.

To work around this, keep a software copy of the register instead.  Since
it's not modified from the mpic itself, it's a feasible solution.  Still,
keep it under a config option to avoid wasting memory on other platforms.

Signed-off-by: Olof Johansson 
Signed-off-by: Paul Mackerras

[POWERPC] Add an optional device_node pointer to the irq_host

2007-09-13T15:33:20+00:00

The majority of irq_host implementations (3 out of 4) are associated
with a device_node, and need to stash it somewhere. Rather than having
it somewhere different for each host, add an optional device_node pointer
to the irq_host structure.

Signed-off-by: Michael Ellerman 
Signed-off-by: Paul Mackerras

[POWERPC] MPIC protected sources

2007-07-22T11:30:59+00:00

Some HW platforms, such as the new cell blades, requires some MPIC sources
to be left alone by the operating system. This implements support for
a "protected-sources" property in the mpic controller node containing a list
of source numbers to be protected against operating system interference.

For those interested in the gory details, the MPIC on the southbridge of
those blades has some of the processor outputs routed to the cell, and
at least one routed as a GPIO to the service processor. It will be used
in the GA product for routing some of the southbridge error interrupts
to the service processor which implements some of the RAS stuff, such
as checkstopping when fatal errors occurs before they can propagate.

Signed-off-by: Benjamin Herrenschmidt 
Acked-by: Arnd Bergmann 
Signed-off-by: Paul Mackerras

[POWERPC] Remove warning in mpic.c

2007-05-17T11:11:14+00:00

arch/powerpc/sysdev/mpic.c: In function 'mpic_request_ipis':
arch/powerpc/sysdev/mpic.c:1445: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result

Signed-off-by: Olof Johansson 
Signed-off-by: Paul Mackerras

[POWERPC] MPIC U3/U4 MSI backend

2007-05-08T03:46:48+00:00

MPIC U3/U4 MSI backend. Based on code from Segher, heavily hacked by me.
This only deals with MSI on U3/U4 MPICs, aka. CPC 9x5.

If we find a U3/U4 then we enable this backend, ie. take over the ppc_md
MSI hooks. We might need more elaborate logic in future to decide which
backend is enabled.

We need our own irq_chip so that we can do MSI masking/unmasking on
the device itself. We also need to mask explicitly on shutdown to make
sure we don't get bitten by lazy-disable semantics.

Signed-off-by: Michael Ellerman 
Signed-off-by: Paul Mackerras

[POWERPC] MPIC MSI allocator

2007-05-08T03:43:48+00:00

To support MSI on MPIC we need a way to reserve and allocate hardware irq
numbers, this patch implements an allocator for that purpose.

New firmware platforms must define a "msi-available-ranges" property on their
MPIC node for MSI to work. For U3/U4 we do a best-guess setup.

Signed-off-by: Michael Ellerman 
Signed-off-by: Paul Mackerras

[POWERPC] Enable MSI mappings for MPIC

2007-05-08T03:42:27+00:00

On some Apple machines the HT MSI mappings are not enabled by firmware, so
we need to do it by hand.

We can't use the pci routines as this code runs too early.

Signed-off-by: Michael Ellerman 
Signed-off-by: Paul Mackerras