linux.git/arch/powerpc/kernel/misc_32.S, branch v2.6.24

[POWERPC] 4xx: Deal with 44x virtually tagged icache

2007-11-01T12:15:30+00:00

The 44x family has an interesting "feature" which is a virtually
tagged instruction cache (yuck !). So far, we haven't dealt with
it properly, which means we've been mostly lucky or people didn't
report the problems, unless people have been running custom patches
in their distro...

This is an attempt at fixing it properly. I chose to do it by
setting a global flag whenever we change a PTE that was previously
marked executable, and flush the entire instruction cache upon
return to user space when that happens.

This is a bit heavy handed, but it's hard to do more fine grained
flushes as the icbi instruction, on those processor, for some very
strange reasons (since the cache is virtually mapped) still requires
a valid TLB entry for reading in the target address space, which
isn't something I want to deal with.

Signed-off-by: Benjamin Herrenschmidt 
Signed-off-by: Josh Boyer

[POWERPC] 4xx: Fix 4xx flush_tlb_page()

2007-11-01T12:15:09+00:00

On 4xx CPUs, the current implementation of flush_tlb_page() uses
a low level _tlbie() assembly function that only works for the
current PID. Thus, invalidations caused by, for example, a COW
fault triggered by get_user_pages() from a different context will
not work properly, causing among other things, gdb breakpoints
to fail.

This patch adds a "pid" argument to _tlbie() on 4xx processors,
and uses it to flush entries in the right context. FSL BookE
also gets the argument but it seems they don't need it (their
tlbivax form ignores the PID when invalidating according to the
document I have).

Signed-off-by: Benjamin Herrenschmidt 
Acked-by: Kumar Gala 
Signed-off-by: Josh Boyer

[POWERPC] Fix small race in 44x tlbie function

2007-08-15T05:12:50+00:00

The 440 family of processors don't have a tlbie instruction.  So, we
implement TLB invalidates by explicitly searching the TLB with tlbsx.,
then clobbering the relevant entry, if any.  Unfortunately the PID for
the search needs to be stored in the MMUCR register, which is also
used by the TLB miss handler.  Interrupts were enabled in _tlbie(), so
an interrupt between loading the MMUCR and the tlbsx could cause
incorrect search results, and thus a failure to invalide TLB entries
which needed to be invalidated.

This fixes the problem in both arch/ppc and arch/powerpc by inhibiting
interrupts (even critical and debug interrupts) across the relevant
instructions.

Signed-off-by: David Gibson 
Acked-by: Josh Boyer 
Signed-off-by: Paul Mackerras

[POWERPC] Merge CPU features pertaining to icache coherency

2007-06-14T12:30:16+00:00

Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially).  It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.

In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).

This tries to clarify the situation a little.  The COHERENT_ICACHE
feature becomes availble on 32-bit and is set for all CPUs where i and
d-cache are effectively coherent, whether this is due to special logic
(POWER5) or because they're unified.  We check this, instead of
SPLIT_ID_CACHE nearly everywhere.

The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200.  In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature.  The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.

This will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.

Signed-off-by: David Gibson 
Signed-off-by: Paul Mackerras

[POWERPC] Remove _get_SP

2007-03-22T11:52:58+00:00

We already have an inline __get_SP, no need for yet another one.

Signed-off-by: Anton Blanchard 
Signed-off-by: Paul Mackerras

[POWERPC] Consolidate feature fixup code

2006-10-25T01:42:10+00:00

There are currently two versions of the functions for applying the
feature fixups, one for CPU features and one for firmware features. In
addition, they are both in assembly and with separate implementations
for 32 and 64 bits. identify_cpu() is also implemented in assembly and
separately for 32 and 64 bits.

This patch replaces them with a pair of C functions. The call sites are
slightly moved on ppc64 as well to be called from C instead of from
assembly, though it's a very small change, and thus shouldn't cause any
problem.

Signed-off-by: Benjamin Herrenschmidt 
Acked-by: Olof Johansson 
Signed-off-by: Paul Mackerras

[PATCH] rename the provided execve functions to kernel_execve

2006-10-02T14:57:23+00:00

Some architectures provide an execve function that does not set errno, but
instead returns the result code directly.  Rename these to kernel_execve to
get the right semantics there.  Moreover, there is no reasone for any of these
architectures to still provide __KERNEL_SYSCALLS__ or _syscallN macros, so
remove these right away.

[akpm@osdl.org: build fix]
[bunk@stusta.de: build fix]
Signed-off-by: Arnd Bergmann 
Cc: Andi Kleen 
Acked-by: Paul Mackerras 
Cc: Benjamin Herrenschmidt 
Cc: Richard Henderson 
Cc: Ivan Kokshaysky 
Cc: Russell King 
Cc: Ian Molton 
Cc: Mikael Starvik 
Cc: David Howells 
Cc: Yoshinori Sato 
Cc: Hirokazu Takata 
Cc: Ralf Baechle 
Cc: Kyle McMartin 
Cc: Heiko Carstens 
Cc: Martin Schwidefsky 
Cc: Paul Mundt 
Cc: Kazumoto Kojima 
Cc: Richard Curnow 
Cc: William Lee Irwin III 
Cc: "David S. Miller" 
Cc: Jeff Dike 
Cc: Paolo 'Blaisorblade' Giarrusso 
Cc: Miles Bader 
Cc: Chris Zankel 
Cc: "Luck, Tony" 
Cc: Geert Uytterhoeven 
Cc: Roman Zippel 
Signed-off-by: Adrian Bunk 
Cc: Arnd Bergmann 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

Remove obsolete #include

2006-06-30T17:25:36+00:00

Signed-off-by: Jörn Engel 
Signed-off-by: Adrian Bunk

[POWERPC] Consolidate some of kernel/misc*.S

2006-06-28T05:19:00+00:00

There were some common functions (mainly i/o).

Also some small white space cleanups and remove a couple of small unused
functions.

Signed-off-by: Stephen Rothwell 
Signed-off-by: Paul Mackerras

[PATCH] powerpc: remove do-nothing cpu setup routines

2006-05-19T04:24:18+00:00

Removed the do-nothing routines __setup_cpu_power3 and
__setup_cpu_power4 and replaced them with a null pointer check
in the caller.  Also removed the Cell processor specific
routine __setup_cpu_be which improperly accessed the
hypervisor page size configuration at SPR HID6.

Signed-off-by: Geoff Levand 
Signed-off-by: Paul Mackerras