linux.git/arch/powerpc/kernel/entry_64.S, branch v2.6.20

[POWERPC] Fix manual assembly WARN_ON() in enter_rtas().

2007-01-09T06:03:02+00:00

When we switched over to the generic BUG mechanism we forgot to change
the assembly code which open-codes a WARN_ON() in enter_rtas(), so the
bug table got corrupted.

This patch provides an EMIT_BUG_ENTRY macro for use in assembly code,
and uses it in entry_64.S. Tested with CONFIG_DEBUG_BUGVERBOSE on ppc64
but not without -- I tried to turn it off but it wouldn't go away; I
suspect Aunt Tillie probably needed it.

This version gets __FILE__ and __LINE__ right in the assembly version --
rather than saying include/asm-powerpc/bug.h line 21 every time which is
a little suboptimal.

Signed-off-by: David Woodhouse 
Signed-off-by: Paul Mackerras

[POWERPC] iSeries: Eliminate "exceeds stub group size" warnings

2006-12-04T09:41:31+00:00

Commit 3ccfc65c5004e5fe5cfbffe43b8acc686680b53e missed the same fixes for
legacy iSeries specific code, so make some more symbols no longer global.

Signed-off-by: Stephen Rothwell 
Signed-off-by: Paul Mackerras

[PATCH] Remove occurences of PPC_MULTIPLATFORM in head_64.S

2006-11-13T03:44:58+00:00

Since iSeries is merged to MULTIPLATFORM, there is no way to build a 64bit
kernel without MULTIPLATFORM, so PPC_MULTIPLATFORM can be removed in
64bit-only files.

Signed-off-by: Sascha Hauer 
Acked-by: Benjamin Herrenschmidt 
Signed-off-by: Paul Mackerras

[POWERPC] Make sure interrupt enable gets restored properly

2006-10-18T00:12:53+00:00

The lazy IRQ disable patch missed a couple of places where the
interrupt enable flags need to be restored correctly.  First, we
weren't restoring the paca->hard_enabled flag on interrupt exit.
Instead of saving it on entry, we compute it from the MSR_EE bit
in the MSR we are restoring at exit.  Secondly, the MMU hash miss
code was clearing both paca->soft_enabled and paca->hard_enabled
but not restoring them in the case where hash_page was able to
resolve the miss from the Linux page tables.

Signed-off-by: Paul Mackerras

[POWERPC] Lazy interrupt disabling for 64-bit machines

2006-10-16T06:31:36+00:00

This implements a lazy strategy for disabling interrupts.  This means
that local_irq_disable() et al. just clear the 'interrupts are
enabled' flag in the paca.  If an interrupt comes along, the interrupt
entry code notices that interrupts are supposed to be disabled, and
clears the EE bit in SRR1, clears the 'interrupts are hard-enabled'
flag in the paca, and returns.  This means that interrupts only
actually get disabled in the processor when an interrupt comes along.

When interrupts are enabled by local_irq_enable() et al., the code
sets the interrupts-enabled flag in the paca, and then checks whether
interrupts got hard-disabled.  If so, it also sets the EE bit in the
MSR to hard-enable the interrupts.

This has the potential to improve performance, and also makes it
easier to make a kernel that can boot on iSeries and on other 64-bit
machines, since this lazy-disable strategy is very similar to the
soft-disable strategy that iSeries already uses.

This version renames paca->proc_enabled to paca->soft_enabled, and
changes a couple of soft-disables in the kexec code to hard-disables,
which should fix the crash that Michael Ellerman saw.  This doesn't
yet use a reserved CR field for the soft_enabled and hard_enabled
flags.  This applies on top of Stephen Rothwell's patches to make it
possible to build a combined iSeries/other kernel.

Signed-off-by: Paul Mackerras

[POWERPC] implement BEGIN/END_FW_FTR_SECTION

2006-10-03T06:50:21+00:00

and use it an all the obvious places in assembler code.

Signed-off-by: Stephen Rothwell

[POWERPC] SLB shadow buffer cleanup

2006-08-25T03:17:08+00:00

Cleanup some of the #define magic as suggested by Milton.

Signed-off-by: Michael Neuling 
Signed-off-by: Paul Mackerras

[POWERPC] Implement SLB shadow buffer

2006-08-08T07:08:56+00:00

This adds a shadow buffer for the SLBs and regsiters it with PHYP.
Only the bolted SLB entries (top 3) are shadowed.

The SLB shadow buffer tells the hypervisor what the kernel needs to
have in the SLB for the kernel to be able to function.  The hypervisor
can use this information to speed up partition context switches.

Signed-off-by: Michael Neuling 
Signed-off-by: Paul Mackerras

Remove obsolete #include

2006-06-30T17:25:36+00:00

Signed-off-by: Jörn Engel 
Signed-off-by: Adrian Bunk

[POWERPC] system call micro optimisation

2006-06-15T09:31:26+00:00

In the syscall path we currently have:

       crclr   so
       mfcr    r9

If we shift the crclr up we can avoid a stall on some CPUs.

Signed-off-by: Anton Blanchard 
Signed-off-by: Paul Mackerras