linux.git/arch/powerpc/kernel/cputable.c, branch v3.14

powerpc/book3s: Flush SLB/TLBs if we get SLB/TLB machine check errors on power8.

2013-12-05T05:04:40+00:00

This patch handles the memory errors on power8. If we get a machine check
exception due to SLB or TLB errors, then flush SLBs/TLBs and reload SLBs to
recover.

Signed-off-by: Mahesh Salgaonkar 
Acked-by: Paul Mackerras 
Signed-off-by: Benjamin Herrenschmidt

powerpc/book3s: Flush SLB/TLBs if we get SLB/TLB machine check errors on power7.

2013-12-05T05:04:39+00:00

If we get a machine check exception due to SLB or TLB errors, then flush
SLBs/TLBs and reload SLBs to recover. We do this in real mode before turning
on MMU. Otherwise we would run into nested machine checks.

If we get a machine check when we are in guest, then just flush the
SLBs and continue. This patch handles errors for power7. The next
patch will handle errors for power8

Signed-off-by: Mahesh Salgaonkar 
Signed-off-by: Paul Mackerras 
Signed-off-by: Benjamin Herrenschmidt

powerpc/book3s: Add flush_tlb operation in cpu_spec.

2013-12-05T05:04:38+00:00

This patch introduces flush_tlb operation in cpu_spec structure. This will
help us to invoke appropriate CPU-side flush tlb routine. This patch
adds the foundation to invoke CPU specific flush routine for respective
architectures. Currently this patch introduce flush_tlb for p7 and p8.

Signed-off-by: Mahesh Salgaonkar 
Acked-by: Paul Mackerras 
Signed-off-by: Benjamin Herrenschmidt

Merge remote-tracking branch 'scott/next' into next

2013-08-09T06:01:40+00:00

Merge some Freescale updates from Scott Wood

powerpc/perf: add 2 additional performance monitor counters for e6500 core

2013-08-07T23:38:03+00:00

There are 6 counters in e6500 core instead of 4 in e500 core.

Signed-off-by: Lijun Pan 
Signed-off-by: Scott Wood

powerpc: Add second POWER8 PVR entry

2013-07-24T04:18:43+00:00

POWER8 comes with two different PVRs.  This patch enables the additional
PVR in the cputable.

The existing entry (PVR=0x4b) is renamed to POWER8E and the new entry
(PVR=0x4d) is given POWER8.

Signed-off-by: Michael Neuling 
Signed-off-by: Benjamin Herrenschmidt

powerpc/power8: Fix oprofile and perf

2013-06-09T22:36:19+00:00

In 2ac6f42 powerpc/cputable: Fix oprofile_cpu_type on power8
we broke all power8 hw events.

This reverts this change and uses oprofile_type instead. Perf now works
on POWER8 again and oprofile will revert to using timers on POWER8.

Kudos to mpe this fix.

Signed-off-by: Michael Neuling 
Signed-off-by: Benjamin Herrenschmidt

powerpc/cputable: Fix typo on P7+ cputable entry

2013-05-31T23:30:03+00:00

Fix a typo in setting COMMON_USER2_POWER7 bits to .cpu_user_features2
cpu specs table.

Signed-off-by: Will Schmidt 
Acked-by: Michael Neuling 
Signed-off-by: Benjamin Herrenschmidt

powerpc/cputable: Fix oprofile_cpu_type on power8

2013-05-31T22:29:25+00:00

Maynard informed me that neither the oprofile kernel module nor oprofile
userspace has been updated to support that "legacy" oprofile module
interface for power8, which is indicated by "ppc64/power8." This results
in no samples. The solution is to default to the "timer" type, instead.
The raw entry also should be updated, as "ppc64/ibm-compat-v1" indicates
to oprofile userspace to use "compatibility events" which are obsolete
in ISA 2.07.

Signed-off-by: Nishanth Aravamudan 
Signed-off-by: Benjamin Herrenschmidt

powerpc/cputable: Advertise support for ISEL/HTM/DSCR/TAR on POWER8

2013-05-05T23:25:40+00:00

Signed-off-by: Nishanth Aravamudan 
Signed-off-by: Benjamin Herrenschmidt