linux.git/arch/powerpc/kernel/cputable.c, branch v2.6.24

[POWERPC] 4xx: Workaround for the 440EP(x)/GR(x) processors identical PVR issue.

2007-11-01T12:13:43+00:00

PowerPC 440EP(x) 440GR(x) processors have the same PVR values, since
they have identical cores. However, FPU is not supported on GR(x) and
enabling APU instruction broadcast in the CCR0 register (to enable FPU)
may cause unpredictable results. There's no safe way to detect FPU
support at runtime. This patch provides a workarund for the issue.

We use a POWER6 "logical PVR approach". First, we identify all EP(x)
and GR(x) processors as GR(x) ones (which is safe). Then we check
the device tree cpu path. If we have a EP(x) processor entry,
we call identify_cpu again with PVR | 0x8. This bit is always 0
in the real PVR. This way we enable FPU only for 440EP(x).

Signed-off-by: Valentine Barshak 
Signed-off-by: Josh Boyer

[POWERPC] 4xx: Add AMCC 405EX support to cputable.c

2007-10-11T20:01:22+00:00

Signed-off-by: Stefan Roese 
Signed-off-by: Josh Boyer

[POWERPC] Fix performance monitor on machines with logical PVR

2007-10-11T11:37:50+00:00

Some IBM machines supply a "logical" PVR (processor version register)
value in the device tree in the cpu nodes rather than the real PVR.
This is used for instance to indicate that the processors in a POWER6
partition have been configured by the hypervisor to run in POWER5+
mode rather than POWER6 mode.  To cope with this, we call identify_cpu
a second time with the logical PVR value (the first call is with the
real PVR value in the very early setup code).

However, POWER5+ machines can also supply a logical PVR value, and use
the same value (the value that indicates a v2.04 architecture
compliant processor).  This causes problems for code that uses the
performance monitor (such as oprofile), because the PMU registers are
different in POWER6 (even in POWER5+ mode) from the real POWER5+.

This change works around this problem by taking out the PMU
information from the cputable entries for the logical PVR values, and
changing identify_cpu so that the second call to it won't overwrite
the PMU information that was established by the first call (the one
with the real PVR), but does update the other fields.  Specifically,
if the cputable entry for the logical PVR value has num_pmcs == 0,
none of the PMU-related fields get used.

So that we can create a mixed cputable entry, we now make cur_cpu_spec
point to a single static struct cpu_spec, and copy stuff from
cpu_specs[i] into it.  This has the side-effect that we can now make
cpu_specs[] be initdata.

Ultimately it would be good to move the PMU-related fields out to a
separate structure, pointed to by the cputable entries, and change
identify_cpu so that it saves the PMU info pointer, copies the whole
structure, and restores the PMU info pointer, rather than identify_cpu
having to list all the fields that are *not* PMU-related.

Signed-off-by: Paul Mackerras 
Acked-by: Benjamin Herrenschmidt

[POWERPC] 4xx: 440EPx/GRx incorrect write to DDR SDRAM errata workaround

2007-10-03T12:20:18+00:00

Add a workaround for PowerPC 440EPx/GRx incorrect write to
DDR SDRAM errata. Data can be written to wrong address
in SDRAM when write pipelining enabled on plb0. We disable
it in the cpu_setup for these processors at early init.

Signed-off-by: Valentine Barshak 
Signed-off-by: Josh Boyer

[POWERPC] 4xx: Move 440EP(x) FPU setup from head_44x to cpu_setup_4xx

2007-10-03T12:20:17+00:00

The PowerPC 440EP(x) FPU init is currently done in head_44x
under ifdefs. Since we should support more then one board
in the same kernel, we move FPU initialization code from head_44x
to cpu_setup_44x and add cpu_setup callbacks for 440EP(x).

Signed-off-by: Valentine Barshak 
Signed-off-by: Josh Boyer

[POWERPC] 4xx: Introduce cpu_setup functionality to 44x platform

2007-10-03T12:20:17+00:00

This adds cpu_setup functionality for ppc44x platform.
Low level cpu-spefic initialization routines should be
placed in cpu_setup_44x.S and a callback should be
added to cputable. The cpu_setup is invoked
by identify_cpu() function at early init.

Signed-off-by: Valentine Barshak 
Signed-off-by: Josh Boyer

[POWERPC] Add cpu feature for SPE handling

2007-09-14T13:53:30+00:00

Make it so that SPE support can be determined at runtime.  This is similiar
to how we handle AltiVec.  This allows us to have SPE support built in and
work on processors with and without SPE.

Signed-off-by: Kumar Gala

[POWERPC] PowerPC 440EPx: Sequoia board support

2007-09-07T12:49:13+00:00

AMCC PPC440EPx Sequoia board support.

Signed-off-by: Valentine Barshak 
Acked-by: David Gibson 
Signed-off-by: Josh Boyer

[POWERPC] Oprofile support for Power 5++

2007-07-11T03:21:46+00:00

This adds a new oprofile cpu type for Power 5 revision 3 chips.
The new name is ppc64/power5++ and is used so that the performance
counters can be set up correctly.

Signed-off-by: Mike Wolf 
Signed-off-by: Paul Mackerras

[POWERPC] Add cputable entry for PowerPC 440SPe Rev. B

2007-07-10T11:53:44+00:00

When adding the cputable entry for 440SPe Rev. B, we also need to
adjust the existing entries for 440SP Rev. A and 440SPe Rev. B so that
they look more bits of the PVR.  The 440SPe Rev. B has PVR 53421891,
which would match the current 440SP Rev. A pattern of 53xxx891.  To
distinguish between 440SP and 440SPe, we need to use the first three
digits of the PVR, which are respectively 532 and 534.

Signed-off-by: Roland Dreier 
Signed-off-by: Paul Mackerras