linux.git/arch/powerpc/kernel/cpu_setup_power.S, branch v3.10

powerpc: Fix TLB cleanup at boot on POWER8

2013-05-24T08:13:44+00:00

The TLB has 512 congruence classes (2048 entries 4 way set associative)
while P7 had 128

Signed-off-by: Benjamin Herrenschmidt

powerpc: Turn on the EBB H/FSCR bits

2013-05-02T00:36:55+00:00

This turns Event Based Branching (EBB) on in the Hypervisor Facility Status and
Control Register (HFSCR) and Facility Status and Control Register (FSCR).

Signed-off-by: Michael Neuling 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Setup BHRB instructions facility in HFSCR for POWER8

2013-05-02T00:35:15+00:00

Make BHRB instructions available in problem and privileged states.

Signed-off-by: Anshuman Khandual 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Initialise PMU related regs on Power8

2013-04-26T06:11:06+00:00

For both HV and guest kernels, intialise PMU regs to something sane.

Signed-off-by: Michael Ellerman 
Acked-by: Paul Mackerras 
Signed-off-by: Benjamin Herrenschmidt

powerpc/power8: Fix secondary CPUs hanging on boot for HV=0

2013-04-26T06:08:17+00:00

In __restore_cpu_power8 we determine if we are HV and if not, we return
before setting HV only resources.

Unfortunately we forgot to restore the link register from r11 before
returning.

This will happen on boot and with secondary CPUs not coming online.

This adds the missing link register restore.

Signed-off-by: Michael Neuling 
CC: 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Setup in HFSCR for POWER8

2013-04-18T03:03:59+00:00

Setup the HFSCR (Hypervisor Facility Status and Control Register) for POWER8
when running HV=1.  The HFSCR is the same as the FSCR except it's for
hypervisors.  It controls the available of various facilities in OS and
userspace levels.  It also indicates the cause of a hypervisor facility
unavailable interrupt (although we are not using this here).

This patch sets the facilities Linux knows about incase the firmware doesn't.

Signed-off-by: Michael Neuling 
Signed-off-by: Michael Ellerman

powerpc: Set DSCR bit in FSCR setup

2013-03-05T05:56:30+00:00

We support DSCR (Data Stream Control Register) so we should make sure we set it
in the FSCR (Facility Status & Control Register) incase some firmwares don't
set it.  If we don't set this, we'll take a facility unavailable exception when
using the DSCR.

Signed-off-by: Michael Neuling 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Fix setting FSCR for HV=0 and on secondary CPUs

2013-03-05T05:56:29+00:00

Currently we only set the FSCR (Facility Status and Control Register) when HV=1
but this feature is available when HV=0 also.  This patch sets FSCR when HV=0.

Also, we currently only set the FSCR on the master CPU.  This patch also sets
the FSCR on secondary CPUs.

Signed-off-by: Michael Neuling 
cc: Ian Munsie 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Add support for context switching the TAR register

2013-02-08T03:05:50+00:00

This patch adds support for enabling and context switching the Target
Address Register in Power8. The TAR is a new special purpose register
that can be used for computed branches with the bctar[l] (branch
conditional to TAR) instruction in the same manner as the count and link
registers.

Signed-off-by: Ian Munsie 
Signed-off-by: Matt Evans 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Setup relocation on exceptions for bare metal systems

2012-11-15T04:08:06+00:00

This turns on MMU on execptions via AIL field in the LPCR.

Signed-off-by: Matt Evans 
Signed-off-by: Michael Neuling 
Signed-off-by: Benjamin Herrenschmidt