linux.git/arch/powerpc/kernel/cpu_setup_44x.S, branch v2.6.26

[POWERPC] 4xx: Fix 460GT support to not enable FPU

2008-04-24T18:32:47+00:00

The AMCC 460GT doesn't have an FPU so let's not enable support for it.

Signed-off-by: Stefan Roese 
Signed-off-by: Josh Boyer

[POWERPC] 4xx: Add AMCC 460EX/460GT support to cputable.c & cpu_setup_44x.S

2008-03-26T12:19:16+00:00

This patch adds basic support for the AMCC 460EX/460GT PPC's to arch/powerpc.
Currently those PPC's are still based on a 440 core and *not* a 460 core.

Here some basic features of those SoC's:

460EX:
- Up to 1.2GHz, 32kB L1 I-cache and D-cache, 256kB L2-cache, FPU
- 1 * PCI (max 66MHz), 2 * PCIe (one 4-lane, one 1-lane)
- 2 * GBit Ethernet with TCP/IP acceleration
- USB 2.0 Host/Device OTG and Host interface
- SATA controller
- Optional security feature

460GT (only changes to 460EX):
- 4 * GBit Ethernet with TCP/IP acceleration
- RapidIO
- No SATA
- No USB

Signed-off-by: Stefan Roese 
Signed-off-by: Josh Boyer

[POWERPC] 4xx: Fix 440grx setup function to call 440A fixup

2007-12-23T19:27:37+00:00

The mechanism to do the setup for 440A cores changed recently.  This fixes
the 440grx setup function to call __fixup_440A_mcheck.

Signed-off-by: Josh Boyer

[POWERPC] Reworking machine check handling and Fix 440/440A

2007-12-23T19:11:59+00:00

This adds a cputable function pointer for the CPU-side machine
check handling. The semantic is still the same as the old one,
the one in ppc_md. overrides the one in cputable, though
ultimately we'll want to change that so the CPU gets first.

This removes CONFIG_440A which was a problem for multiplatform
kernels and instead fixes up the IVOR at runtime from a setup_cpu
function. The "A" version of the machine check also tweaks the
regs->trap value to differenciate the 2 versions at the C level.

Signed-off-by: Benjamin Herrenschmidt 
Signed-off-by: Josh Boyer

[POWERPC] 4xx: 440EPx/GRx incorrect write to DDR SDRAM errata workaround

2007-10-03T12:20:18+00:00

Add a workaround for PowerPC 440EPx/GRx incorrect write to
DDR SDRAM errata. Data can be written to wrong address
in SDRAM when write pipelining enabled on plb0. We disable
it in the cpu_setup for these processors at early init.

Signed-off-by: Valentine Barshak 
Signed-off-by: Josh Boyer

[POWERPC] 4xx: Move 440EP(x) FPU setup from head_44x to cpu_setup_4xx

2007-10-03T12:20:17+00:00

The PowerPC 440EP(x) FPU init is currently done in head_44x
under ifdefs. Since we should support more then one board
in the same kernel, we move FPU initialization code from head_44x
to cpu_setup_44x and add cpu_setup callbacks for 440EP(x).

Signed-off-by: Valentine Barshak 
Signed-off-by: Josh Boyer

[POWERPC] 4xx: Introduce cpu_setup functionality to 44x platform

2007-10-03T12:20:17+00:00

This adds cpu_setup functionality for ppc44x platform.
Low level cpu-spefic initialization routines should be
placed in cpu_setup_44x.S and a callback should be
added to cputable. The cpu_setup is invoked
by identify_cpu() function at early init.

Signed-off-by: Valentine Barshak 
Signed-off-by: Josh Boyer