linux.git/arch/powerpc/include/asm/ppc-opcode.h, branch v2.6.35

powerpc/85xx: Make sure lwarx hint isn't set on ppc32

2010-03-17T04:24:06+00:00

e500v1/v2 based chips will treat any reserved field being set in an
opcode as illegal.  Thus always setting the hint in the opcode is
a bad idea.

Anton should be kept away from the powerpc opcode map.

Signed-off-by: Kumar Gala

powerpc: Use lwarx/ldarx hint in bit locks

2010-02-17T03:03:15+00:00

This patch implements the lwarx/ldarx hint bit for bit locks.

Signed-off-by: Anton Blanchard 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Use lwarx hint in spinlocks

2010-02-17T03:03:14+00:00

Recent versions of the PowerPC architecture added a hint bit to the larx
instructions to differentiate between an atomic operation and a lock operation:

> 0 Other programs might attempt to modify the word in storage addressed by EA
> even if the subsequent Store Conditional succeeds.
>
> 1 Other programs will not attempt to modify the word in storage addressed by
> EA until the program that has acquired the lock performs a subsequent store
> releasing the lock.

To avoid a binutils dependency this patch create macros for the extended lwarx
format and uses it in the spinlock code. To test this change I used a simple
test case that acquires and releases a global pthread mutex:

	pthread_mutex_lock(&mutex);
	pthread_mutex_unlock(&mutex);

On a 32 core POWER6, running 32 test threads we spend almost all our time in
the futex spinlock code:

    94.37%     perf  [kernel]                     [k] ._raw_spin_lock
               |
               |--99.95%-- ._raw_spin_lock
               |          |
               |          |--63.29%-- .futex_wake
               |          |
               |          |--36.64%-- .futex_wait_setup

Which is a good test for this patch. The results (in lock/unlock operations per
second) are:

before: 1538203 ops/sec
after:  2189219 ops/sec

An improvement of 42%

A 32 core POWER7 improves even more:

before: 1279529 ops/sec
after:  2282076 ops/sec

An improvement of 78%

Signed-off-by: Anton Blanchard 
Signed-off-by: Benjamin Herrenschmidt

powerpc/mm: Add opcode definitions for tlbivax and tlbsrx.

2009-08-20T00:12:38+00:00

This adds the opcode definitions to ppc-opcode.h for the two instructions
tlbivax and tlbsrx. as defined by Book3E 2.06

Signed-off-by: Benjamin Herrenschmidt

powerpc: Add 2.06 tlbie mnemonics

2009-05-21T05:44:21+00:00

This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.

Only useful for bare metal systems.

Signed-off-by: Milton Miller 
Signed-off-by: Michael Neuling 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Move VSX load/stores into ppc-opcode.h

2009-05-21T05:44:21+00:00

Cleans up the VSX load/store instructions by moving them into
ppc-opcode.h.

Signed-off-by: Michael Neuling 
Acked-by: Kumar Gala 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Cleanup macros in ppc-opcode.h

2009-05-21T05:44:21+00:00

Make macros more braces happy.

Signed-off-by: Michael Neuling 
Acked-by: Kumar Gala 
Signed-off-by: Benjamin Herrenschmidt

Revert "powerpc: Add support for early tlbilx opcode"

2009-04-23T13:51:22+00:00

This reverts commit e9965577406a2148ade97b5e0ce7c448b4ba4ef6.  Our HW
guys were able to fix this so it never sees the light of day.

Signed-off-by: Kumar Gala

powerpc: Add support for early tlbilx opcode

2009-04-07T06:36:30+00:00

During the ISA 2.06 development the opcode for tlbilx changed and some
early implementations used to old opcode.  Add support for a MMU_FTR
fixup to deal with this.

Signed-off-by: Kumar Gala

powerpc: Fix tlbilx opcode

2009-04-07T06:36:27+00:00

The tlbilx opcode was not matching the Power ISA 2.06 arch spec.
The old opcode was an early suggested opcode that changed during the
2.06 architecture process.

Signed-off-by: Kumar Gala