linux.git/arch/parisc/kernel, branch v3.11

parisc: Fix interrupt routing for C8000 serial ports

2013-07-31T21:42:32+00:00

We can't use dev->mod_index for selecting the interrupt routing entry,
because it's not an index into interrupt routing table. It will be even
wrong on a machine with 2 CPUs (4 cores). But all needed information is
contained in the PAT entries for the serial ports. mod[0] contains the
iosapic address and mod_info has some indications for the interrupt
input (at least it looks like it). This patch implements the searching
for the right iosapic and uses this interrupt input information.

Signed-off-by: Thomas Bogendoerfer 
Cc:  # 3.10
Signed-off-by: Helge Deller

parisc: Remove arch/parisc/kernel/sys32.h header

2013-07-31T21:42:21+00:00

The KERNEL_SYSCALL define is not used anymore so the header can be
removed.

Signed-off-by: John David Anglin 
Signed-off-by: Helge Deller

parisc: Fix cache routines to ignore vma's with an invalid pfn

2013-07-31T21:41:47+00:00

The parisc architecture does not have a pte special bit. As a result,
special mappings are handled with the VM_PFNMAP and VM_MIXEDMAP flags.
VM_MIXEDMAP mappings may or may not have a "struct page" backing. When
pfn_valid() is false, there is no "struct page" backing. Otherwise, they
are treated as normal pages.

The FireGL driver uses the VM_MIXEDMAP without a backing "struct page".
This treatment caused a panic due to a TLB data miss in
update_mmu_cache. This appeared to be in the code generated for
page_address(). We were in fact using a very circular bit of code to
determine the physical address of the PFN in various cache routines.
This wasn't valid when there was no "struct page" backing.  The needed
address can in fact be determined simply from the PFN itself without
using the "struct page".

The attached patch updates update_mmu_cache(), flush_cache_mm(),
flush_cache_range() and flush_cache_page() to check pfn_valid() and to
directly compute the PFN physical and virtual addresses.

Signed-off-by: John David Anglin 
Cc:  # 3.10
Signed-off-by: Helge Deller

parisc: delete __cpuinit usage from all users

2013-07-14T23:36:51+00:00

The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications.  For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.

After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out.  Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.

This removes all the parisc uses of the __cpuinit macros.

[1] https://lkml.org/lkml/2013/5/20/589

Acked-by: James Bottomley 
Cc: Helge Deller 
Cc: linux-parisc@vger.kernel.org
Signed-off-by: Paul Gortmaker

parisc: Ensure volatile space register %sr1 is not clobbered

2013-07-09T20:09:22+00:00

I still see the occasional random segv on rp3440.  Looking at one of
these (a code 15), it appeared the problem must be with the cache
handling of anonymous pages.  Reviewing this, I noticed that the space
register %sr1 might be being clobbered when we flush an anonymous page.

Register %sr1 is used for TLB purges in a couple of places.  These
purges are needed on PA8800 and PA8900 processors to ensure cache
consistency of flushed cache lines.

The solution here is simply to move the %sr1 load into the TLB lock
region needed to ensure that one purge executes at a time on SMP
systems.  This was already the case for one use.  After a few days of
operation, I haven't had a random segv on my rp3440.

Signed-off-by: John David Anglin 
Cc:  # 3.10
Signed-off-by: Helge Deller

parisc: more capabilities info in /proc/cpuinfo

2013-07-09T20:09:17+00:00

Signed-off-by: Helge Deller 
Cc:  # 3.10

Merge 3.10-rc7 into tty-next

2013-06-24T22:17:53+00:00

We want the tty fixes in this branch as well.

Signed-off-by: Greg Kroah-Hartman

parisc: Use unshadowed index register for flush instructions in flush_dcache_page_asm and flush_icache_page_asm

2013-06-18T18:29:10+00:00

The comment at the start of pacache.S states that the base and index
registers used for fdc,fic, and pdc instructions should not use shadowed
registers. Although this is probably unnecessary for tmpalias flushes,
there is also no reason not to comply.

Signed-off-by: John David Anglin 
Signed-off-by: Helge Deller

parisc: provide pci_mmap_page_range() for parisc

2013-06-18T18:29:08+00:00

pci_mmap_page_range() is needed for X11-server support on C8000 with ATI
FireGL card.

Signed-off-by Thomas Bogendoerfer 
Signed-off-by: Helge Deller

parisc: fix serial ports on C8000 workstation

2013-06-18T18:29:07+00:00

The C8000 workstation (64 bit kernel only) has a somewhat different
serial port configuration than other models.
Thomas Bogendoerfer sent a patch to fix this in September 2010, which
was now minimally modified by me.

Signed-off-by: Thomas Bogendoerfer 
Signed-off-by: Helge Deller