linux.git/arch/parisc/kernel/cache.c, branch v5.10

parisc: Rewrite tlb flush threshold calculation

2020-10-15T06:10:39+00:00

Signed-off-by: John David Anglin 
Signed-off-by: Helge Deller

mm: remove unneeded includes of

2020-08-07T18:33:26+00:00

Patch series "mm: cleanup usage of "

Most architectures have very similar versions of pXd_alloc_one() and
pXd_free_one() for intermediate levels of page table.  These patches add
generic versions of these functions in  and enable
use of the generic functions where appropriate.

In addition, functions declared and defined in  headers are
used mostly by core mm and early mm initialization in arch and there is no
actual reason to have the  included all over the place.
The first patch in this series removes unneeded includes of


In the end it didn't work out as neatly as I hoped and moving
pXd_alloc_track() definitions to  would require
unnecessary changes to arches that have custom page table allocations, so
I've decided to move lib/ioremap.c to mm/ and make pgalloc-track.h local
to mm/.

This patch (of 8):

In most cases  header is required only for allocations of
page table memory.  Most of the .c files that include that header do not
use symbols declared in  and do not require that header.

As for the other header files that used to include , it is
possible to move that include into the .c file that actually uses symbols
from  and drop the include from the header file.

The process was somewhat automated using

	sed -i -E '/[<"]asm\/pgalloc\.h/d' \
                $(grep -L -w -f /tmp/xx \
                        $(git grep -E -l '[<"]asm/pgalloc\.h'))

where /tmp/xx contains all the symbols defined in
arch/*/include/asm/pgalloc.h.

[rppt@linux.ibm.com: fix powerpc warning]

Signed-off-by: Mike Rapoport 
Signed-off-by: Andrew Morton 
Reviewed-by: Pekka Enberg 
Acked-by: Geert Uytterhoeven 	[m68k]
Cc: Abdul Haleem 
Cc: Andy Lutomirski 
Cc: Arnd Bergmann 
Cc: Christophe Leroy 
Cc: Joerg Roedel 
Cc: Max Filippov 
Cc: Peter Zijlstra 
Cc: Satheesh Rajendran 
Cc: Stafford Horne 
Cc: Stephen Rothwell 
Cc: Steven Rostedt 
Cc: Joerg Roedel 
Cc: Matthew Wilcox 
Link: http://lkml.kernel.org/r/20200627143453.31835-1-rppt@kernel.org
Link: http://lkml.kernel.org/r/20200627143453.31835-2-rppt@kernel.org
Signed-off-by: Linus Torvalds

parisc: use pgtable-nopXd instead of 4level-fixup

2019-12-05T03:44:15+00:00

parisc has two or three levels of page tables and can use appropriate
pgtable-nopXd and folding of the upper layers.

Replace usage of include/asm-generic/4level-fixup.h and explicit
definitions of __PAGETABLE_PxD_FOLDED in parisc with
include/asm-generic/pgtable-nopmd.h for two-level configurations and
with include/asm-generic/pgtable-nopud.h for three-lelve configurations
and adjust page table manipulation macros and functions accordingly.

Link: http://lkml.kernel.org/r/1572938135-31886-9-git-send-email-rppt@kernel.org
Signed-off-by: Mike Rapoport 
Acked-by: Helge Deller 
Cc: Anatoly Pugachev 
Cc: Anton Ivanov 
Cc: Arnd Bergmann 
Cc: "David S. Miller" 
Cc: Geert Uytterhoeven 
Cc: Greentime Hu 
Cc: Greg Ungerer 
Cc: "James E.J. Bottomley" 
Cc: Jeff Dike 
Cc: "Kirill A. Shutemov" 
Cc: Mark Salter 
Cc: Matt Turner 
Cc: Michal Simek 
Cc: Peter Rosin 
Cc: Richard Weinberger 
Cc: Rolf Eike Beer 
Cc: Russell King 
Cc: Russell King 
Cc: Sam Creasey 
Cc: Vincent Chen 
Cc: Vineet Gupta 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

parisc: Avoid spurious inequivalent alias kernel error messages

2019-11-04T07:34:27+00:00

This patch changes flush_dcache_page() to only print inequivalent alias error
messages on systems that require coherency.  Inequivalent aliases can occur on
systems that don't require coherency and this can cause spurious messages.

Signed-off-by: John David Anglin 
Signed-off-by: Helge Deller

parisc: Use __ro_after_init in cache.c

2019-05-10T19:00:44+00:00

Signed-off-by: Helge Deller

parisc: Use per-pagetable spinlock

2019-05-03T21:47:41+00:00

PA-RISC uses a global spinlock to protect pagetable updates in the TLB
fault handlers. When multiple cores are taking TLB faults simultaneously,
the cache line containing the spinlock becomes a bottleneck.

This patch embeds the spinlock in the top level page directory, so that
every process has its own lock. It improves performance by 30% when
doing parallel compilations.

At least on the N class systems, only one PxTLB inter processor
broadcast can be active at any one time on the Merced bus. If a Merced
bus is found, this patch serializes the TLB flushes with the
pa_tlb_flush_lock spinlock.

v1: Initial patch by Mikulas
v2: Added Merced detection by Helge
v3: Revised TLB serialization by Dave & Helge

Signed-off-by: Mikulas Patocka 
Signed-off-by: John David Anglin 
Signed-off-by: Helge Deller

parisc: Optimze cache flush algorithms

2018-10-20T19:10:26+00:00

The attached patch implements three optimizations:

1) Loops in flush_user_dcache_range_asm, flush_kernel_dcache_range_asm,
purge_kernel_dcache_range_asm, flush_user_icache_range_asm, and
flush_kernel_icache_range_asm are unrolled to reduce branch overhead.

2) The static branch prediction for cmpb instructions in pacache.S have
been reviewed and the operand order adjusted where necessary.

3) For flush routines in cache.c, we purge rather flush when we have no
context.  The pdc instruction at level 0 is not required to write back
dirty lines to memory. This provides a performance improvement over the
fdc instruction if the feature is implemented.

Version 2 adds alternative patching.

The patch provides an average improvement of about 2%.

Signed-off-by: John David Anglin 
Signed-off-by: Helge Deller

parisc: Add alternative coding infrastructure

2018-10-17T15:22:26+00:00

This patch adds the necessary code to patch a running kernel at runtime
to improve performance.

The current implementation offers a few optimizations variants:

- When running a SMP kernel on a single UP processor, unwanted assembler
  statements like locking functions are overwritten with NOPs. When
  multiple instructions shall be skipped, one branch instruction is used
  instead of multiple nop instructions.

- In the UP case, some pdtlb and pitlb instructions are patched to
  become pdtlb,l and pitlb,l which only flushes the CPU-local tlb
  entries instead of broadcasting the flush to other CPUs in the system
  and thus may improve performance.

- fic and fdc instructions are skipped if no I- or D-caches are
  installed.  This should speed up qemu emulation and cacheless systems.

- If no cache coherence is needed for IO operations, the relevant fdc
  and sync instructions in the sba and ccio drivers are replaced by
  nops.

- On systems which share I- and D-TLBs and thus don't have a seperate
  instruction TLB, the pitlb instruction is replaced by a nop.

Live-patching is done early in the boot process, just after having run
the system inventory. No drivers are running and thus no external
interrupts should arrive. So the hope is that no TLB exceptions will
occur during the patching. If this turns out to be wrong we will
probably need to do the patching in real-mode.

Signed-off-by: Helge Deller

parisc: Reorder TLB flush timing calculation

2018-10-17T06:18:00+00:00

On boot (mostly reboot), my c8000 sometimes crashes after it prints the
TLB flush threshold.  The lockup is hard.  The front LED flashes red and
the box must be unplugged to reset the error.

I noticed that when the crash occurs the TLB flush threshold is about
one quarter what it is on a successful boot.  If I disabled the
calculation, the crash didn't occur.  There also seemed to be a timing
dependency affecting the crash.  I finally realized that the
flush_tlb_all() timing test runs just after the secondary CPUs are
started.  There seems to be a problem with running flush_tlb_all() too
soon after the CPUs are started.

The timing for the range test always seemed okay.  So, I reversed the
order of the two timing tests and I haven't had a crash at this point so
far.

I added a couple of information messages which I have left to help with
diagnosis if the problem should appear on another machine.

This version reduces the minimum TLB flush threshold to 16 KiB.

Signed-off-by: John David Anglin 
Signed-off-by: Helge Deller

parisc: Move cache flush functions into .text.hot section

2018-04-11T09:40:35+00:00

and move the disable_sr_hashing() C and assembly functions into the
.init section.

Signed-off-by: Helge Deller