linux.git/arch/openrisc/kernel/sync-timer.c, branch v7.0 Linux kernel source tree openrisc: add tick timer multi-core sync logic 2017-11-03T05:01:16+00:00 Stafford Horne shorne@gmail.com 2017-07-06T21:06:30+00:00 4553474d977d1ee8a81067cfbc588f1df84ce3e9 In case timers are not in sync when cpus start (i.e. hot plug / offset resets) we need to synchronize the secondary cpus internal timer with the main cpu. This is needed as in OpenRISC SMP there is only one clocksource registered which reads from the same ttcr register on each cpu. This synchronization routine heavily borrows from mips implementation that does something similar. Signed-off-by: Stafford Horne <shorne@gmail.com> 
In case timers are not in sync when cpus start (i.e. hot plug / offset
resets) we need to synchronize the secondary cpus internal timer with
the main cpu.  This is needed as in OpenRISC SMP there is only one
clocksource registered which reads from the same ttcr register on each
cpu.

This synchronization routine heavily borrows from mips implementation that
does something similar.

Signed-off-by: Stafford Horne <shorne@gmail.com>