linux.git/arch/openrisc/kernel/smp.c, branch v6.2

profile: setup_profiling_timer() is moslty not implemented

2022-07-30T01:12:36+00:00

The setup_profiling_timer() is mostly un-implemented by many
architectures.  In many places it isn't guarded by CONFIG_PROFILE which is
needed for it to be used.  Make it a weak symbol in kernel/profile.c and
remove the 'return -EINVAL' implementations from the kenrel.

There are a couple of architectures which do return 0 from the
setup_profiling_timer() function but they don't seem to do anything else
with it.  To keep the /proc compatibility for now, leave these for a
future update or removal.

On ARM, this fixes the following sparse warning:
arch/arm/kernel/smp.c:793:5: warning: symbol 'setup_profiling_timer' was not declared. Should it be static?

Link: https://lkml.kernel.org/r/20220721195509.418205-1-ben-linux@fluff.org
Signed-off-by: Ben Dooks 
Signed-off-by: Andrew Morton

Merge tag 'for-linus' of git://github.com/openrisc/linux

2021-11-08T17:31:25+00:00

Pull OpenRISC updates from Stafford Horne:
 "This includes two minor cleanups, plus a bug fix for OpenRISC TLB
  flush code that allows the the SMP kernel to boot again"

* tag 'for-linus' of git://github.com/openrisc/linux:
  openrisc: fix SMP tlb flush NULL pointer dereference
  openrisc: signal: remove unused DEBUG_SIG macro
  openrisc: time: don't mark comment as kernel-doc

openrisc: fix SMP tlb flush NULL pointer dereference

2021-11-03T11:48:29+00:00

Throughout the OpenRISC kernel port VMA is passed as NULL when flushing
kernel tlb entries.  Somehow this was missed when I was testing
c28b27416da9 ("openrisc: Implement proper SMP tlb flushing") and now the
SMP kernel fails to completely boot.

In OpenRISC VMA is used only to determine which cores need to have their
TLB entries flushed.

This patch updates the logic to flush tlbs on all cores when the VMA is
passed as NULL.  Also, we update places VMA is passed as NULL to use
flush_tlb_kernel_range instead.  Now, the only place VMA is passed as
NULL is in the implementation of flush_tlb_kernel_range.

Fixes: c28b27416da9 ("openrisc: Implement proper SMP tlb flushing")
Reported-by: Jan Henrik Weinstock 
Signed-off-by: Stafford Horne

openrisc: Use of_get_cpu_hwid()

2021-10-20T18:37:24+00:00

Replace open coded parsing of CPU nodes' 'reg' property with
of_get_cpu_hwid().

Cc: Jonas Bonn 
Cc: Stefan Kristiansson 
Cc: Stafford Horne 
Cc: openrisc@lists.librecores.org
Signed-off-by: Rob Herring 
Acked-by: Stafford Horne 
Link: https://lore.kernel.org/r/20211006164332.1981454-7-robh@kernel.org

sched/core: Initialize the idle task with preemption disabled

2021-05-12T11:01:45+00:00

As pointed out by commit

  de9b8f5dcbd9 ("sched: Fix crash trying to dequeue/enqueue the idle thread")

init_idle() can and will be invoked more than once on the same idle
task. At boot time, it is invoked for the boot CPU thread by
sched_init(). Then smp_init() creates the threads for all the secondary
CPUs and invokes init_idle() on them.

As the hotplug machinery brings the secondaries to life, it will issue
calls to idle_thread_get(), which itself invokes init_idle() yet again.
In this case it's invoked twice more per secondary: at _cpu_up(), and at
bringup_cpu().

Given smp_init() already initializes the idle tasks for all *possible*
CPUs, no further initialization should be required. Now, removing
init_idle() from idle_thread_get() exposes some interesting expectations
with regards to the idle task's preempt_count: the secondary startup always
issues a preempt_disable(), requiring some reset of the preempt count to 0
between hot-unplug and hotplug, which is currently served by
idle_thread_get() -> idle_init().

Given the idle task is supposed to have preemption disabled once and never
see it re-enabled, it seems that what we actually want is to initialize its
preempt_count to PREEMPT_DISABLED and leave it there. Do that, and remove
init_idle() from idle_thread_get().

Secondary startups were patched via coccinelle:

  @begone@
  @@

  -preempt_disable();
  ...
  cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);

Signed-off-by: Valentin Schneider 
Signed-off-by: Ingo Molnar 
Acked-by: Peter Zijlstra 
Link: https://lore.kernel.org/r/20210512094636.2958515-1-valentin.schneider@arm.com

openrisc: Use devicetree to determine present cpus

2021-02-08T20:38:50+00:00

Use the device tree to determine the present cpus instead of assuming
all CONFIG_NRCPUS are actually present in the system.

Signed-off-by: Jan Henrik Weinstock 
[shorne: Squashed 2 email commits and added summary from email]
Cc: Geert Uytterhoeven 
Signed-off-by: Stafford Horne

openrisc: Implement proper SMP tlb flushing

2020-08-04T01:59:45+00:00

Up until now when flushing pages from the TLB on SMP OpenRISC was always
resorting to flush the entire TLB on all CPUs.  This patch adds the
mechanics for flushing specific ranges and pages based on the usage.

The function switch_mm is updated to account for cpu usage by updating
mm_struct's cpumask.  This is used in the SMP flush routines.

This mostly follows the riscv implementation.

Signed-off-by: Stafford Horne

openrisc: use mmgrab

2020-01-31T13:21:21+00:00

Mmgrab was introduced in commit f1f1007644ff ("mm: add new mmgrab()
helper") and most of the kernel was updated to use it. Update a
remaining file.

The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)


@@ expression e; @@
- atomic_inc(&e->mm_count);
+ mmgrab(e);


Signed-off-by: Julia Lawall 
Signed-off-by: Stafford Horne 
[shorne: Added missing sched/mm.h include]

openrisc: fix possible deadlock scenario during timer sync

2017-11-03T05:01:17+00:00

OpenRISC borrows its timer sync logic from MIPS, Matt helped to review
the OpenRISC implementation and noted that we may suffer the same
deadlock case that MIPS has faced. The case being:

  "the MIPS timer synchronization code contained the possibility of
  deadlock. If you mark a CPU online before it goes into the synchronize
  loop, then the boot CPU can schedule a different thread and send IPIs to
  all "online" CPUs. It gets stuck waiting for the secondary to ack it's
  IPI, since this secondary CPU has not enabled IRQs yet, and is stuck
  waiting for the master to synchronise with it.  The system then
  deadlocks."

Fix this by moving set_cpu_online() to after timer sync.

Reported-by: Matt Redfearn 
Signed-off-by: Stafford Horne

openrisc: add tick timer multi-core sync logic

2017-11-03T05:01:16+00:00

In case timers are not in sync when cpus start (i.e. hot plug / offset
resets) we need to synchronize the secondary cpus internal timer with
the main cpu.  This is needed as in OpenRISC SMP there is only one
clocksource registered which reads from the same ttcr register on each
cpu.

This synchronization routine heavily borrows from mips implementation that
does something similar.

Signed-off-by: Stafford Horne