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<title>linux.git/arch/openrisc/kernel/entry.S, branch v6.6</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>openrisc: Support floating point user api</title>
<updated>2023-04-26T14:08:06+00:00</updated>
<author>
<name>Stafford Horne</name>
<email>shorne@gmail.com</email>
</author>
<published>2023-04-14T07:27:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=27267655c5313ba0f5a3caa9ad35d887d9a12574'/>
<id>27267655c5313ba0f5a3caa9ad35d887d9a12574</id>
<content type='text'>
Add support for handling floating point exceptions and forwarding the
SIGFPE signal to processes.  Also, add fpu state to sigcontext.

Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
<content type='xhtml'>
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<pre>
Add support for handling floating point exceptions and forwarding the
SIGFPE signal to processes.  Also, add fpu state to sigcontext.

Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>openrisc: Support storing and restoring fpu state</title>
<updated>2023-04-26T14:08:06+00:00</updated>
<author>
<name>Stafford Horne</name>
<email>shorne@gmail.com</email>
</author>
<published>2023-04-14T07:25:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=63d7f9f11e5e81de2ce8f1c7a8aaed5b0288eddf'/>
<id>63d7f9f11e5e81de2ce8f1c7a8aaed5b0288eddf</id>
<content type='text'>
OpenRISC floating point state is not so expensive to save as OpenRISC uses
general purpose registers for floating point instructions.  We need to save
only the floating point status and control register, FPCSR.

Add support to maintain the FPCSR unconditionally upon exceptions and
switches.  On machines that do not support FPU this will always just
store 0x0 and restore is a no-op.  On FPU systems this adds an
additional special purpose register read/write and read/write to memory
(already cached).

Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
OpenRISC floating point state is not so expensive to save as OpenRISC uses
general purpose registers for floating point instructions.  We need to save
only the floating point status and control register, FPCSR.

Add support to maintain the FPCSR unconditionally upon exceptions and
switches.  On machines that do not support FPU this will always just
store 0x0 and restore is a no-op.  On FPU systems this adds an
additional special purpose register read/write and read/write to memory
(already cached).

Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>openrisc: Properly store r31 to pt_regs on unhandled exceptions</title>
<updated>2023-04-26T14:08:06+00:00</updated>
<author>
<name>Stafford Horne</name>
<email>shorne@gmail.com</email>
</author>
<published>2023-02-11T10:14:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=812489ac4dd91144a74ce65ecf232252a2e406fb'/>
<id>812489ac4dd91144a74ce65ecf232252a2e406fb</id>
<content type='text'>
In commit 91993c8c2ed5 ("openrisc: use shadow registers to save regs on
exception") the unhandled exception path was changed to do an early
store of r30 instead of r31.  The entry code was not updated and r31 is
not getting stored to pt_regs.

This patch updates the entry handler to store r31 instead of r30.  We
also remove some misleading commented out store r30 and r31
instructrions.

I noticed this while working on adding floating point exception
handling,  This issue probably would never impact anything since we kill
the process or Oops right away on unhandled exceptions.

Fixes: 91993c8c2ed5 ("openrisc: use shadow registers to save regs on exception")
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In commit 91993c8c2ed5 ("openrisc: use shadow registers to save regs on
exception") the unhandled exception path was changed to do an early
store of r30 instead of r31.  The entry code was not updated and r31 is
not getting stored to pt_regs.

This patch updates the entry handler to store r31 instead of r30.  We
also remove some misleading commented out store r30 and r31
instructrions.

I noticed this while working on adding floating point exception
handling,  This issue probably would never impact anything since we kill
the process or Oops right away on unhandled exceptions.

Fixes: 91993c8c2ed5 ("openrisc: use shadow registers to save regs on exception")
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>openrisc: Add syscall details to emergency syscall debugging</title>
<updated>2022-05-23T08:15:49+00:00</updated>
<author>
<name>Stafford Horne</name>
<email>shorne@gmail.com</email>
</author>
<published>2022-01-30T08:38:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=a0a94bc9a68ffad0cecae6dbff53e5486cdb8eb0'/>
<id>a0a94bc9a68ffad0cecae6dbff53e5486cdb8eb0</id>
<content type='text'>
When bringing linux on the or1k Marocchino we ran into issues starting
init.  This patch adds the syscall number and return address to
assist tracing syscalls even before strace is able to be used.

By default this is all disabled but a developer could adjust the ifdef
to enable debugging.

Cc: Andrey Bacherov &lt;bandvig@mail.ru&gt;
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
When bringing linux on the or1k Marocchino we ran into issues starting
init.  This patch adds the syscall number and return address to
assist tracing syscalls even before strace is able to be used.

By default this is all disabled but a developer could adjust the ifdef
to enable debugging.

Cc: Andrey Bacherov &lt;bandvig@mail.ru&gt;
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>openrisc: Add clone3 ABI wrapper</title>
<updated>2021-12-04T02:12:09+00:00</updated>
<author>
<name>Stafford Horne</name>
<email>shorne@gmail.com</email>
</author>
<published>2021-12-03T22:10:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=433fe39f674d58bc7a3e8254a5d2ffc290b7e04e'/>
<id>433fe39f674d58bc7a3e8254a5d2ffc290b7e04e</id>
<content type='text'>
Like fork and clone the clone3 syscall needs a wrapper to save callee
saved registers, which is required by the OpenRISC ABI.  This came up
after auditing code following a discussion with Rob Landley and Arnd
Bergmann [0].

Tested with the clone3 kselftests and there were no issues.

[0] https://lore.kernel.org/all/41206fc7-f8ce-98aa-3718-ba3e1431e320@landley.net/T/#m9c0cdb2703813b9df4da04cf6b30de1f1aa89944

Fixes: 07e83dfbe16c ("openrisc: Enable the clone3 syscall")
Cc: Rob Landley &lt;rob@landley.net&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Like fork and clone the clone3 syscall needs a wrapper to save callee
saved registers, which is required by the OpenRISC ABI.  This came up
after auditing code following a discussion with Rob Landley and Arnd
Bergmann [0].

Tested with the clone3 kselftests and there were no issues.

[0] https://lore.kernel.org/all/41206fc7-f8ce-98aa-3718-ba3e1431e320@landley.net/T/#m9c0cdb2703813b9df4da04cf6b30de1f1aa89944

Fixes: 07e83dfbe16c ("openrisc: Enable the clone3 syscall")
Cc: Rob Landley &lt;rob@landley.net&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>openrisc: Use delay slot for clone and fork wrappers</title>
<updated>2021-12-04T02:12:09+00:00</updated>
<author>
<name>Stafford Horne</name>
<email>shorne@gmail.com</email>
</author>
<published>2021-12-03T13:56:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=07baf50ac754384b9ea996f82b9a2a8aba946aa4'/>
<id>07baf50ac754384b9ea996f82b9a2a8aba946aa4</id>
<content type='text'>
This saves one instruction.

Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This saves one instruction.

Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>openrisc: Cleanup switch code and comments</title>
<updated>2021-12-04T02:12:09+00:00</updated>
<author>
<name>Stafford Horne</name>
<email>shorne@gmail.com</email>
</author>
<published>2021-12-03T13:42:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=840b66c2550df04fbd66d8be782efa23649a0163'/>
<id>840b66c2550df04fbd66d8be782efa23649a0163</id>
<content type='text'>
The saving of the r12 register was there for a compiler bug referring
to a port that was never upstreamed.  It should be safe to use this
as the new compiler is what we use and the old deprecated.

Also, clean up some typos and references to old names in the switch
comments.

Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The saving of the r12 register was there for a compiler bug referring
to a port that was never upstreamed.  It should be safe to use this
as the new compiler is what we use and the old deprecated.

Also, clean up some typos and references to old names in the switch
comments.

Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>irq: openrisc: perform irqentry in entry code</title>
<updated>2021-10-26T09:13:28+00:00</updated>
<author>
<name>Mark Rutland</name>
<email>mark.rutland@arm.com</email>
</author>
<published>2021-10-20T10:31:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=418360b23113d62aa99586ada37806b4a7a53afa'/>
<id>418360b23113d62aa99586ada37806b4a7a53afa</id>
<content type='text'>
In preparation for removing HANDLE_DOMAIN_IRQ_IRQENTRY, have
arch/openrisc perform all the irqentry accounting in its entry code. As
arch/openrisc uses GENERIC_IRQ_MULTI_HANDLER, we can use
generic_handle_arch_irq() to do so.

There should be no functional change as a result of this patch.

Signed-off-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Reviewed-by: Marc Zyngier &lt;maz@kernel.org&gt;
Reviewed-by: Stafford Horne &lt;shorne@gmail.com&gt;
Cc: Jonas Bonn &lt;jonas@southpole.se&gt;
Cc: Stefan Kristiansson &lt;stefan.kristiansson@saunalahti.fi&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In preparation for removing HANDLE_DOMAIN_IRQ_IRQENTRY, have
arch/openrisc perform all the irqentry accounting in its entry code. As
arch/openrisc uses GENERIC_IRQ_MULTI_HANDLER, we can use
generic_handle_arch_irq() to do so.

There should be no functional change as a result of this patch.

Signed-off-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Reviewed-by: Marc Zyngier &lt;maz@kernel.org&gt;
Reviewed-by: Stafford Horne &lt;shorne@gmail.com&gt;
Cc: Jonas Bonn &lt;jonas@southpole.se&gt;
Cc: Stefan Kristiansson &lt;stefan.kristiansson@saunalahti.fi&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'for-linus' of git://github.com/openrisc/linux</title>
<updated>2021-09-03T18:03:00+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2021-09-03T18:03:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=603eefda5fcf8f9dab3ae253e677abb285f6f3bc'/>
<id>603eefda5fcf8f9dab3ae253e677abb285f6f3bc</id>
<content type='text'>
Pull OpenRISC updates from Stafford Horne:
 "A few cleanups and compiler warning fixes for OpenRISC.

  Also, this includes dts and defconfig updates to enable Ethernet on
  OpenRISC/Litex FPGA SoC's now that the LiteEth driver has gone
  upstream"

* tag 'for-linus' of git://github.com/openrisc/linux:
  openrisc/litex: Update defconfig
  openrisc/litex: Add ethernet device
  openrisc/litex: Update uart address
  openrisc: Fix compiler warnings in setup
  openrisc: rename or32 code &amp; comments to or1k
  openrisc: don't printk() unconditionally
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull OpenRISC updates from Stafford Horne:
 "A few cleanups and compiler warning fixes for OpenRISC.

  Also, this includes dts and defconfig updates to enable Ethernet on
  OpenRISC/Litex FPGA SoC's now that the LiteEth driver has gone
  upstream"

* tag 'for-linus' of git://github.com/openrisc/linux:
  openrisc/litex: Update defconfig
  openrisc/litex: Add ethernet device
  openrisc/litex: Update uart address
  openrisc: Fix compiler warnings in setup
  openrisc: rename or32 code &amp; comments to or1k
  openrisc: don't printk() unconditionally
</pre>
</div>
</content>
</entry>
<entry>
<title>openrisc: rename or32 code &amp; comments to or1k</title>
<updated>2021-08-05T01:53:59+00:00</updated>
<author>
<name>Randy Dunlap</name>
<email>rdunlap@infradead.org</email>
</author>
<published>2021-07-16T02:23:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=11648cbb7b335b7eb54e1ff973fb938939616f46'/>
<id>11648cbb7b335b7eb54e1ff973fb938939616f46</id>
<content type='text'>
From Documentation/openrisc/todo.rst, rename "or32" in the
source code to "or1k" since this is the name that has been
settled on.

Signed-off-by: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Cc: Jonas Bonn &lt;jonas@southpole.se&gt;
Cc: Stefan Kristiansson &lt;stefan.kristiansson@saunalahti.fi&gt;
Cc: Stafford Horne &lt;shorne@gmail.com&gt;
Cc: openrisc@lists.librecores.org
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
From Documentation/openrisc/todo.rst, rename "or32" in the
source code to "or1k" since this is the name that has been
settled on.

Signed-off-by: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Cc: Jonas Bonn &lt;jonas@southpole.se&gt;
Cc: Stefan Kristiansson &lt;stefan.kristiansson@saunalahti.fi&gt;
Cc: Stafford Horne &lt;shorne@gmail.com&gt;
Cc: openrisc@lists.librecores.org
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</pre>
</div>
</content>
</entry>
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