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<title>linux.git/arch/openrisc/kernel/entry.S, branch v5.1</title>
<subtitle>Linux kernel source tree</subtitle>
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<entry>
<title>openrisc: Fix broken paths to arch/or32</title>
<updated>2018-12-19T15:04:39+00:00</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert@linux-m68k.org</email>
</author>
<published>2018-12-03T12:20:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=57ce8ba0fd3a95bf29ed741df1c52bd591bf43ff'/>
<id>57ce8ba0fd3a95bf29ed741df1c52bd591bf43ff</id>
<content type='text'>
OpenRISC was mainlined as "openrisc", not "or32".
vmlinux.lds is generated from vmlinux.lds.S.

Signed-off-by: Geert Uytterhoeven &lt;geert@linux-m68k.org&gt;
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
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<pre>
OpenRISC was mainlined as "openrisc", not "or32".
vmlinux.lds is generated from vmlinux.lds.S.

Signed-off-by: Geert Uytterhoeven &lt;geert@linux-m68k.org&gt;
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>openrisc: entry: Fix delay slot exception detection</title>
<updated>2018-07-01T07:48:24+00:00</updated>
<author>
<name>Stafford Horne</name>
<email>shorne@gmail.com</email>
</author>
<published>2018-07-01T05:17:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=ae15a41a641449f536578b0d9ec0e4ade130deb5'/>
<id>ae15a41a641449f536578b0d9ec0e4ade130deb5</id>
<content type='text'>
Originally in patch e6d20c55a4 ("openrisc: entry: Fix delay slot
detection") I fixed delay slot detection, but only for QEMU.  We missed
that hardware delay slot detection using delay slot exception flag (DSX)
was still broken.  This was because QEMU set the DSX flag in both
pre-exception supervision register (ESR) and supervision register (SR)
register, but on real hardware the DSX flag is only set on the SR
register during exceptions.

Fix this by carrying the DSX flag into the SR register during exception.
We also update the DSX flag read locations to read the value from the SR
register not the pt_regs SR register which represents ESR.  The ESR
should never have the DSX flag set.

In the process I updated/removed a few comments to match the current
state.  Including removing a comment saying that the DSX detection logic
was inefficient and needed to be rewritten.

I have tested this on QEMU with a patch ensuring it matches the hardware
specification.

Link: https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00000.html
Fixes: e6d20c55a4 ("openrisc: entry: Fix delay slot detection")
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
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<pre>
Originally in patch e6d20c55a4 ("openrisc: entry: Fix delay slot
detection") I fixed delay slot detection, but only for QEMU.  We missed
that hardware delay slot detection using delay slot exception flag (DSX)
was still broken.  This was because QEMU set the DSX flag in both
pre-exception supervision register (ESR) and supervision register (SR)
register, but on real hardware the DSX flag is only set on the SR
register during exceptions.

Fix this by carrying the DSX flag into the SR register during exception.
We also update the DSX flag read locations to read the value from the SR
register not the pt_regs SR register which represents ESR.  The ESR
should never have the DSX flag set.

In the process I updated/removed a few comments to match the current
state.  Including removing a comment saying that the DSX detection logic
was inefficient and needed to be rewritten.

I have tested this on QEMU with a patch ensuring it matches the hardware
specification.

Link: https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00000.html
Fixes: e6d20c55a4 ("openrisc: entry: Fix delay slot detection")
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>openrisc: enable LOCKDEP_SUPPORT and irqflags tracing</title>
<updated>2017-11-03T05:01:16+00:00</updated>
<author>
<name>Stafford Horne</name>
<email>shorne@gmail.com</email>
</author>
<published>2017-07-24T12:55:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=78cdfb5cf15e0f9fb4c2a9176a13a907a1d024f0'/>
<id>78cdfb5cf15e0f9fb4c2a9176a13a907a1d024f0</id>
<content type='text'>
Lockdep is needed for proving the spinlocks and rwlocks work fine on our
platform.  It also requires calling the trace_hardirqs_off() and
trace_hardirqs_on() pair of routines when entering and exiting an
interrupt.

For OpenRISC the interrupt stack frame does not support frame pointers,
so to call trace_hardirqs_on() and trace_hardirqs_off() here the macro's
build up a stack frame each time.

There is one necessary small change in _sys_call_handler to move
interrupt enabling later so they can get re-enabled during syscall
restart. This was done to fix lockdep warnings that are now possible due
to this
patch.

Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
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<pre>
Lockdep is needed for proving the spinlocks and rwlocks work fine on our
platform.  It also requires calling the trace_hardirqs_off() and
trace_hardirqs_on() pair of routines when entering and exiting an
interrupt.

For OpenRISC the interrupt stack frame does not support frame pointers,
so to call trace_hardirqs_on() and trace_hardirqs_off() here the macro's
build up a stack frame each time.

There is one necessary small change in _sys_call_handler to move
interrupt enabling later so they can get re-enabled during syscall
restart. This was done to fix lockdep warnings that are now possible due
to this
patch.

Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>scripts/spelling.txt: add "efective" pattern and fix typo instances</title>
<updated>2017-02-28T02:43:46+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2017-02-27T22:29:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=4e0385dd7469d933c4adf84a617f872ca547aa07'/>
<id>4e0385dd7469d933c4adf84a617f872ca547aa07</id>
<content type='text'>
Fix typos and add the following to the scripts/spelling.txt:

  efective||effective

While we are here, fix the "addres" as well in the touched line in
arch/openrisc/kernel/entry.S.

Link: http://lkml.kernel.org/r/1481573103-11329-10-git-send-email-yamada.masahiro@socionext.com
Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Acked-by: Geert Uytterhoeven &lt;geert@linux-m68k.org&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
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<pre>
Fix typos and add the following to the scripts/spelling.txt:

  efective||effective

While we are here, fix the "addres" as well in the touched line in
arch/openrisc/kernel/entry.S.

Link: http://lkml.kernel.org/r/1481573103-11329-10-git-send-email-yamada.masahiro@socionext.com
Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Acked-by: Geert Uytterhoeven &lt;geert@linux-m68k.org&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>scripts/spelling.txt: add "aligment" pattern and fix typo instances</title>
<updated>2017-02-28T02:43:46+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2017-02-27T22:28:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=550116d21a656e8b5670073e586315e5a6d12f01'/>
<id>550116d21a656e8b5670073e586315e5a6d12f01</id>
<content type='text'>
Fix typos and add the following to the scripts/spelling.txt:

  aligment||alignment

I did not touch the "N_BYTE_ALIGMENT" macro in
drivers/net/wireless/realtek/rtlwifi/wifi.h to avoid unpredictable
impact.

I fixed "_aligment_handler" in arch/openrisc/kernel/entry.S because
it is surrounded by #if 0 ... #endif.  It is surely safe and I
confirmed "_alignment_handler" is correct.

I also fixed the "controler" I found in the same hunk in
arch/openrisc/kernel/head.S.

Link: http://lkml.kernel.org/r/1481573103-11329-8-git-send-email-yamada.masahiro@socionext.com
Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
<content type='xhtml'>
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<pre>
Fix typos and add the following to the scripts/spelling.txt:

  aligment||alignment

I did not touch the "N_BYTE_ALIGMENT" macro in
drivers/net/wireless/realtek/rtlwifi/wifi.h to avoid unpredictable
impact.

I fixed "_aligment_handler" in arch/openrisc/kernel/entry.S because
it is surrounded by #if 0 ... #endif.  It is surely safe and I
confirmed "_alignment_handler" is correct.

I also fixed the "controler" I found in the same hunk in
arch/openrisc/kernel/head.S.

Link: http://lkml.kernel.org/r/1481573103-11329-8-git-send-email-yamada.masahiro@socionext.com
Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>openrisc: entry: Fix delay slot detection</title>
<updated>2017-02-24T19:31:06+00:00</updated>
<author>
<name>Stafford Horne</name>
<email>shorne@gmail.com</email>
</author>
<published>2017-01-10T14:30:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=e6d20c55a4d94eca419f80f996133f523ecedfe0'/>
<id>e6d20c55a4d94eca419f80f996133f523ecedfe0</id>
<content type='text'>
Use execption SR stored in pt_regs for detection, the current SR is not
correct as the handler is running after return from exception.

Also, The code that checks for a delay slot uses a flag bitmask and then
wants to check if the result is not zero.  The test it implemented was
wrong.

Correct it by changing the test to check result against non zero.

Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
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<pre>
Use execption SR stored in pt_regs for detection, the current SR is not
correct as the handler is running after return from exception.

Also, The code that checks for a delay slot uses a flag bitmask and then
wants to check if the result is not zero.  The test it implemented was
wrong.

Correct it by changing the test to check result against non zero.

Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>openrisc: entry: Whitespace and comment cleanups</title>
<updated>2017-02-24T19:31:05+00:00</updated>
<author>
<name>Stafford Horne</name>
<email>shorne@gmail.com</email>
</author>
<published>2017-01-10T14:13:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=2ead7aba44e973b313fde0e39371363459cc1128'/>
<id>2ead7aba44e973b313fde0e39371363459cc1128</id>
<content type='text'>
Cleanups to whitespace and add some comments. Reading through the delay
slot logic I noticed some things:
 - Delay slot instructions were not indented
 - Some comments are not lined up
 - Use tabs and spaces consistent with other code

No functional change

Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Cleanups to whitespace and add some comments. Reading through the delay
slot logic I noticed some things:
 - Delay slot instructions were not indented
 - Some comments are not lined up
 - Use tabs and spaces consistent with other code

No functional change

Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>openrisc: add l.lwa/l.swa emulation</title>
<updated>2017-02-06T12:50:43+00:00</updated>
<author>
<name>Stefan Kristiansson</name>
<email>stefan.kristiansson@saunalahti.fi</email>
</author>
<published>2014-11-03T12:28:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=63104c06a9eddf53f88f6d16196bb036c62967b2'/>
<id>63104c06a9eddf53f88f6d16196bb036c62967b2</id>
<content type='text'>
This adds an emulation layer for implementations
that lack the l.lwa and l.swa instructions.
It handles these instructions both in kernel space and
user space.

Signed-off-by: Stefan Kristiansson &lt;stefan.kristiansson@saunalahti.fi&gt;
[shorne@gmail.com: Added delay slot pc adjust logic]
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
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<pre>
This adds an emulation layer for implementations
that lack the l.lwa and l.swa instructions.
It handles these instructions both in kernel space and
user space.

Signed-off-by: Stefan Kristiansson &lt;stefan.kristiansson@saunalahti.fi&gt;
[shorne@gmail.com: Added delay slot pc adjust logic]
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>openrisc: include l.swa in check for write data pagefault</title>
<updated>2016-12-12T14:10:26+00:00</updated>
<author>
<name>Stefan Kristiansson</name>
<email>stefan.kristiansson@saunalahti.fi</email>
</author>
<published>2014-07-03T17:46:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=cdb75442fedff8cc3ddedbe6e41d00b471634e17'/>
<id>cdb75442fedff8cc3ddedbe6e41d00b471634e17</id>
<content type='text'>
During page fault handling we check the last instruction to understand
if the fault was for a read or for a write.  By default we fall back to
read.  New instructions were added to the openrisc 1.1 spec for an
atomic load/store pair (l.lwa/l.swa).

This patch adds the opcode for l.swa (0x33) allowing it to be treated as
a write operation.

Signed-off-by: Stefan Kristiansson &lt;stefan.kristiansson@saunalahti.fi&gt;
[shorne@gmail.com: expanded a bit on the comment]
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
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<pre>
During page fault handling we check the last instruction to understand
if the fault was for a read or for a write.  By default we fall back to
read.  New instructions were added to the openrisc 1.1 spec for an
atomic load/store pair (l.lwa/l.swa).

This patch adds the opcode for l.swa (0x33) allowing it to be treated as
a write operation.

Signed-off-by: Stefan Kristiansson &lt;stefan.kristiansson@saunalahti.fi&gt;
[shorne@gmail.com: expanded a bit on the comment]
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>openrisc: restore all regs on rt_sigreturn</title>
<updated>2016-12-12T14:09:16+00:00</updated>
<author>
<name>Jonas Bonn</name>
<email>jonas@southpole.se</email>
</author>
<published>2013-09-23T10:04:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=c79902190f7e61fcae7c3f4b613c75062f385678'/>
<id>c79902190f7e61fcae7c3f4b613c75062f385678</id>
<content type='text'>
Fix signal handling for when signals are handled as the result of timers
or exceptions, previous code assumed syscalls. This was noticeable with X
crashing where it uses SIGALRM.

This patch restores all regs before returning to userspace via
_resume_userspace instead of via syscall return path.

The rt_sigreturn syscall is more like a context switch than a function
call; it entails a return from one context (the signal handler) to another
(the process in question).  For a context switch like this there are
effectively no call-saved regs that remain constant across the transition.

Reported-by: Sebastian Macke &lt;sebastian@macke.de&gt;
Signed-off-by: Jonas Bonn &lt;jonas@southpole.se&gt;
Tested-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
[shorne@gmail.com: Updated comment better reflect change and issue]
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Fix signal handling for when signals are handled as the result of timers
or exceptions, previous code assumed syscalls. This was noticeable with X
crashing where it uses SIGALRM.

This patch restores all regs before returning to userspace via
_resume_userspace instead of via syscall return path.

The rt_sigreturn syscall is more like a context switch than a function
call; it entails a return from one context (the signal handler) to another
(the process in question).  For a context switch like this there are
effectively no call-saved regs that remain constant across the transition.

Reported-by: Sebastian Macke &lt;sebastian@macke.de&gt;
Signed-off-by: Jonas Bonn &lt;jonas@southpole.se&gt;
Tested-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
[shorne@gmail.com: Updated comment better reflect change and issue]
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</pre>
</div>
</content>
</entry>
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