linux.git/arch/mips, branch v3.7-rc5

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

2012-10-18T18:49:39+00:00

Pull MIPS fixes from Ralf Baechle:
 "Random small fixes across the MIPS code."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: CMP: Fix physical core number calculation logic
  MIPS: JZ4740: Forward declare struct uart_port in header.
  MIPS: JZ4740: Fix '#include guard' in serial.h
  MIPS: hugetlbfs: Fix hazard between tlb write and pagemask restoration.
  MIPS: Restore pagemask after dumping the TLB.
  MIPS: Hugetlbfs: Handle huge pages correctly in pmd_bad()
  MIPS: R5000: Fix TLB hazard handling.
  MIPS: tlbex: Deal with re-definition of label
  MIPS: Make __{,n,u}delay declarations match definitions and generic delay.h

MIPS: CMP: Fix physical core number calculation logic

2012-10-18T09:45:41+00:00

The CPUNum Field in EBase register is 10bit wide, so after 1 bit right
shift, the mask value should be 0x1ff.

Signed-off-by: jerin jacob 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4420/
Signed-off-by: Ralf Baechle

MIPS: JZ4740: Forward declare struct uart_port in header.

2012-10-17T15:00:50+00:00

As suggested by Geert Uytterhoeven .

Signed-off-by: Ralf Baechle 
Cc: Antony Pavlov 
Cc: linux-mips@linux-mips.org
Cc: Lars-Peter Clausen

MIPS: JZ4740: Fix '#include guard' in serial.h

2012-10-17T14:58:51+00:00

Signed-off-by: Antony Pavlov 
Cc: linux-mips@linux-mips.org
Cc: Lars-Peter Clausen 
Patchwork: https://patchwork.linux-mips.org/patch/4424/
Signed-off-by: Ralf Baechle

UAPI: Place comments in empty arch Kbuilds to make them non-empty

2012-10-17T11:31:16+00:00

Place comments in:

	arch/mips/include/asm/Kbuild
	arch/tile/include/arch/Kbuild

to make them non-empty so that the patch program doesn't remove them when it
reduces them to nothing.

Possibly they should be just deleted, but it's possible that they'll acquire
generic-y or genhdr-y lines in future, so I'm keeping them around for the
moment.

Note that MIPS will compile happily if the file is deleted instead.  I haven't
tested TILE, but I suspect it will be the same there.

Signed-off-by: David Howells 
cc: Ralf Baechle 
cc: Chris Metcalf

MIPS: hugetlbfs: Fix hazard between tlb write and pagemask restoration.

2012-10-16T23:01:21+00:00

On some CPU the write to pagemask might complete before the TLB write
instruction reads from the pagemask register.

Signed-off-by: Ralf Baechle

MIPS: Restore pagemask after dumping the TLB.

2012-10-16T23:01:20+00:00

Or bad things might happen if the last TLB entry isn't a basic size page.

Signed-off-by: Ralf Baechle

MIPS: Hugetlbfs: Handle huge pages correctly in pmd_bad()

2012-10-16T23:01:12+00:00

Signed-off-by: Ralf Baechle

MIPS: R5000: Fix TLB hazard handling.

2012-10-16T20:22:23+00:00

R5000 and the Nevada CPUs (RM5230, RM5231, RM5260, RM5261, RM5270 and
RM5271) are basically the same CPU core and all are documented to require
two instructions separating a write to c0_pagemask, c0_entryhi, c0_entrylo0,
c0_entrylo1 or c0_index.

So far we were only providing on cycle before / after a TLBR/TLBWI
for R5000 but 3 cycles before and 1 cycles after for the Nevadas.

Signed-off-by: Ralf Baechle

MIPS: tlbex: Deal with re-definition of label

2012-10-16T20:21:27+00:00

The microassembler used in tlbex.c does not notice if a label is redefined
resulting in relocations against such labels silently missrelocated.
The issues exists since commit add6eb04776db4189ea89f596cbcde31b899be9d
[Synthesize TLB exception handlers at runtime.] in 2.6.10 and went unnoticed
for so long because the relocations for the affected branches got computed
to do something *almost* sensible.

The issue affects R4000, R4400, QED/IDT RM5230, RM5231, RM5260, RM5261,
RM5270 and RM5271 processors.

Signed-off-by: Ralf Baechle