linux.git/arch/mips, branch v2.6.26 Linux kernel source tree [MIPS] Fix 32bit kernels on R4k with 128 byte cache line size 2008-07-08T18:33:46+00:00 Thomas Bogendoerfer tsbogend@alpha.franken.de 2008-07-08T12:46:34+00:00 14defd90f5281da8a1bf43bc789efbafe5991cd8 The generated copy_page for R4k CPU with a 128 byte cache line size used Create Dirty Exclusive cache line operations even if only part of the cache line was filled. This change avoids generating cache operations, if only part of the cache line size is copied in one loop. It also increases the maxmimum loop size, because the generated code even fits into the available space for r4k CPUs with 128 byte cache line size. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
The generated copy_page for R4k CPU with a 128 byte cache line size used
Create Dirty Exclusive cache line operations even if only part of the
cache line was filled.  This change avoids generating cache operations,
if only part of the cache line size is copied in one loop. It also
increases the maxmimum loop size, because the generated code even fits
into the available space for r4k CPUs with 128 byte cache line size.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Atlas, decstation: Fix section mismatches triggered by defconfigs 2008-07-08T18:33:46+00:00 Shane McDonald mcdonald.shane@gmail.com 2008-07-05T23:19:42+00:00 b32dfbb9c54393af32761add16e249664193621f Resolve these mismatches by defining affected functions with the __cpuinit attribute, rather than __init. Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Resolve these mismatches by defining affected functions with the __cpuinit
attribute, rather than __init.

Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] cevt-txx9: Reset timer counter on initialization 2008-07-03T18:14:27+00:00 Atsushi Nemoto anemo@mba.ocn.ne.jp 2008-06-24T14:26:38+00:00 8986d2f50e1a9ba63f64ccbf59181886aa7898c3 The txx9_tmr_init() will not clear a timer counter register in a certain case. The counter register is cleared on 1->0 transition of TCE bit if CRE=1. So just clearing the TCE bit is not enough. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
The txx9_tmr_init() will not clear a timer counter register in a certain
case.  The counter register is cleared on 1->0 transition of TCE bit if
CRE=1.  So just clearing the TCE bit is not enough.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] IP22: Fix crashes due to wrong L1_CACHE_BYTES 2008-07-03T18:14:27+00:00 Thomas Bogendoerfer tsbogend@alpha.franken.de 2008-06-27T21:52:26+00:00 7e3297dc280f88ec0c6619a895f3d449776f952e The introduction of a real dma cache invalidate makes it important to have a correct cache line size, otherwise the kernel will gives out two memory segment, which might share one cache line. The R4400 Indy/Indigo2 CPU modules are using a second level cache line size of 128 bytes, so MIPS_L1_CACHE_SHIFT needs to be bumped up to 7 for IP22. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
The introduction of a real dma cache invalidate makes it important
to have a correct cache line size, otherwise the kernel will gives
out two memory segment, which might share one cache line. The R4400
Indy/Indigo2 CPU modules are using a second level cache line size
of 128 bytes, so MIPS_L1_CACHE_SHIFT needs to be bumped up to 7 for
IP22.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] IP32: Fix unexpected irq 71 2008-07-03T18:14:27+00:00 Thomas Bogendoerfer tsbogend@alpha.franken.de 2008-06-23T22:48:05+00:00 1faf7f25b2aa4fcd2ae0ec2fd2e9fb9ff4bfee10 It's possible that the crime interrupt handler is called without pending interrupts (probably a hardware issue). To avoid irritating "unexpected irq 71" messages, we now just ignore the spurious crime interrupts. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
It's possible that the crime interrupt handler is called without
pending interrupts (probably a hardware issue). To avoid irritating
"unexpected irq 71" messages, we now just ignore the spurious crime
interrupts.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Au1200: MMC resource size off by one 2008-06-16T14:14:49+00:00 Sergei Shtylyov sshtylyov@ru.mvista.com 2008-05-08T19:06:17+00:00 dab8c6deaf1d654d09c3de8bd4c286d424df255a Au12x0 MMC platform device strangely claims 0x41 bytes for its memory-mapped registers. Make it claim the whole 0x80000 instead according to the memory map given in the datasheets. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Au12x0 MMC platform device strangely claims 0x41 bytes for its
memory-mapped registers.  Make it claim the whole 0x80000 instead according
to the memory map given in the datasheets.

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] TANBAC: Update defconfig 2008-06-16T14:14:49+00:00 Yoichi Yuasa yoichi_yuasa@tripeaks.co.jp 2008-06-16T13:54:16+00:00 b185194ef0691c8068c7d764aa8f78899d05512a These boards need cca setup on CMDLINE. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
These boards need cca setup on CMDLINE.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Vr41xx: Initialize PCI io_map_base 2008-06-16T14:14:48+00:00 Yoichi Yuasa yoichi_yuasa@tripeaks.co.jp 2008-06-16T13:51:08+00:00 f1304b358a6c952e4cd1f92c8a6f183b1026c103 Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Malta: Always compile MTD platform device registration code. 2008-06-16T14:14:48+00:00 Ralf Baechle ralf@linux-mips.org 2008-06-15T23:23:39+00:00 b8157180ccd8bb3752f510c6c434b86394636093 Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Malta: Fix build errors for 64-bit kernels 2008-06-16T14:14:48+00:00 Thomas Bogendoerfer tsbogend@alpha.franken.de 2008-05-29T20:05:07+00:00 938b2b14172bd098972df2a5157bfabf161c90e5 Fix 64-bit Malta by using CKSEG0ADDR and correct casts. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Fix 64-bit Malta by using CKSEG0ADDR and correct casts.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>