The tc35815-mac platform device used a pci bus number and a devfn to identify its target device, but the pci bus number may vary if some bus-bridges are found. Use irq number which is be unique for embedded controllers. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The JMPRS register on Malta boards keeps a 32-bit CPU-endian value. The readw() function assumes that the value it reads is a little-endian 16-bit number. Therefore, using readw() to obtain the value of the JMPRS register is a mistake. This error leads to incorrect reading of the PCI clock frequency on big-endian during board start-up. Change readw() to __raw_readl(). This was tested by injecting a call to printk() and verifying that the value of the jmpr variable was consistent with current setting of the JP4 "PCI CLK" jumper. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Cacheops.h: Fix typo. [MIPS] Cobalt: Qube1 has no serial port so don't use it [MIPS] Cobalt: Fix ethernet interrupts for RaQ1 [MIPS] Kconfig fixes for BCM47XX platform
Because Qube1 doesn't have a serial chip waiting for transmit fifo empty takes forever, which isn't a good idea. No prom_putchar/early console for Qube1 fixes this. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Acked-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
RAQ1 uses the same interrupt routing as Qube2. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The patch below fixes two problems for Kconfig on the BCM47xx platform: - arch/mips/bcm47xx/gpio.c uses ssb_extif_* functions. Selecting SSB_DRIVER_EXTIF makes sure those functions are available. - arch/mips/pci/pci.c needs, when enabled, platform specific functions, which are defined when SSB_PCICORE_HOSTMODE is enabled. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: WANG Cong <xiyou.wangcong@gmail.com> [Ralf: The LDSCRIPT script needed fixing, too] Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
I noticed that the commit f197465384bf7ef1af184c2ed1a4e268911a91e3 (MIPS Tech: Get rid of volatile in core code) broke the software reset functionality for MIPS Malta boards in big-endian mode. According to the MIPS Malta board user's manual, writing the magic 32-bit GORESET value into the SOFTRES register initiates board soft reset. My experimentation has shown that the endianness of the GORESET integer should thereby be the same as the endianness, which has been set for the CPU itself. The writew() function used to write the magic value in the code introduced by the commit mentioned above, however, swaps bytes for big-endian kernels and transfers 16 bits instead of 32. The patch below replaces the writew() function by the __raw_writel() routine, which leaves the byte order intact and transfers the whole MIPS machine word. Trivial code cleanup (replacing spaces by a tab and cutting oversized lines to make checkpatch.pl happy) is also included. The patch was tested using a Malta evaluation board running in both BE and LE modes. For both modes, software reset was fully functional after the change. P.S. I suspect that the same commit broke the "standby" functionality for MIPS Atlas boards. However, I did not touch the Atlas code as I don't have such board at my disposal and also because the linux-mips.org Web site claims that Atlas support is scheduled for removal. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch converts PNX8XXX system timer to clocksource restoring PNX8550 support back to live. Signed-off-by: Vitaly Wool <vitalywool@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>