linux.git/arch/mips/kvm, branch v4.12

KVM: MIPS: Fix maybe-uninitialized build failure

2017-06-20T15:02:48+00:00

This commit fixes a "maybe-uninitialized" build failure in
arch/mips/kvm/tlb.c when KVM, DYNAMIC_DEBUG and JUMP_LABEL are all
enabled. The failure is:

In file included from ./include/linux/printk.h:329:0,
                 from ./include/linux/kernel.h:13,
                 from ./include/asm-generic/bug.h:15,
                 from ./arch/mips/include/asm/bug.h:41,
                 from ./include/linux/bug.h:4,
                 from ./include/linux/thread_info.h:11,
                 from ./include/asm-generic/current.h:4,
                 from ./arch/mips/include/generated/asm/current.h:1,
                 from ./include/linux/sched.h:11,
                 from arch/mips/kvm/tlb.c:13:
arch/mips/kvm/tlb.c: In function ‘kvm_mips_host_tlb_inv’:
./include/linux/dynamic_debug.h:126:3: error: ‘idx_kernel’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
   __dynamic_pr_debug(&descriptor, pr_fmt(fmt), \
   ^~~~~~~~~~~~~~~~~~
arch/mips/kvm/tlb.c:169:16: note: ‘idx_kernel’ was declared here
  int idx_user, idx_kernel;
                ^~~~~~~~~~

There is a similar error relating to "idx_user". Both errors were
observed with GCC 6.

As far as I can tell, it is impossible for either idx_user or idx_kernel
to be uninitialized when they are later read in the calls to kvm_debug,
but to satisfy the compiler, add zero initializers to both variables.

Signed-off-by: James Cowgill 
Fixes: 57e3869cfaae ("KVM: MIPS/TLB: Generalise host TLB invalidate to kernel ASID")
Cc:  # 4.11+
Acked-by: James Hogan 
Signed-off-by: Radim Krčmář

KVM: add kvm_{test,clear}_request to replace {test,clear}_bit

2017-04-27T12:12:22+00:00

Users were expected to use kvm_check_request() for testing and clearing,
but request have expanded their use since then and some users want to
only test or do a faster clear.

Make sure that requests are not directly accessed with bit operations.

Reviewed-by: Christian Borntraeger 
Signed-off-by: Radim Krčmář 
Reviewed-by: Andrew Jones 
Reviewed-by: Cornelia Huck 
Signed-off-by: Paolo Bonzini

kvm: make KVM_CAP_COALESCED_MMIO architecture agnostic

2017-04-07T14:49:00+00:00

Remove code from architecture files that can be moved to virt/kvm, since there
is already common code for coalesced MMIO.

Signed-off-by: Paolo Bonzini 
Reviewed-by: David Hildenbrand 
[Removed a pointless 'break' after 'return'.]
Signed-off-by: Radim Krčmář

KVM: MIPS/Emulate: Properly implement TLBR for T&E

2017-03-28T15:31:37+00:00

Properly implement emulation of the TLBR instruction for Trap & Emulate.
This instruction reads the TLB entry pointed at by the CP0_Index
register into the other TLB registers, which may have the side effect of
changing the current ASID. Therefore abstract the CP0_EntryHi and ASID
changing code into a common function in the process.

A comment indicated that Linux doesn't use TLBR, which is true during
normal use, however dumping of the TLB does use it (for example with the
relatively recent 'x' magic sysrq key), as does a wired TLB entries test
case in my KVM tests.

Signed-off-by: James Hogan 
Acked-by: Ralf Baechle 
Cc: Paolo Bonzini 
Cc: "Radim Krčmář" 
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org

KVM: MIPS/VZ: Handle Octeon III guest.PRid register

2017-03-28T14:36:20+00:00

Octeon III implements a read-only guest CP0_PRid register, so add cases
to the KVM register access API for Octeon to ensure the correct value is
read and writes are ignored.

Signed-off-by: James Hogan 
Cc: Paolo Bonzini 
Cc: "Radim Krčmář" 
Cc: Ralf Baechle 
Cc: David Daney 
Cc: Andreas Herrmann 
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org

KVM: MIPS/VZ: Emulate hit CACHE ops for Octeon III

2017-03-28T14:36:19+00:00

Octeon III doesn't implement the optional GuestCtl0.CG bit to allow
guest mode to execute virtual address based CACHE instructions, so
implement emulation of a few important ones specifically for Octeon III
in response to a GPSI exception.

Currently the main reason to perform these operations is for icache
synchronisation, so they are implemented as a simple icache flush with
local_flush_icache_range().

Signed-off-by: James Hogan 
Cc: Paolo Bonzini 
Cc: "Radim Krčmář" 
Cc: Ralf Baechle 
Cc: David Daney 
Cc: Andreas Herrmann 
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org

KVM: MIPS/VZ: VZ hardware setup for Octeon III

2017-03-28T14:36:18+00:00

Set up hardware virtualisation on Octeon III cores, configuring guest
interrupt routing and carving out half of the root TLB for guest use,
restoring it back again afterwards.

We need to be careful to inhibit TLB shutdown machine check exceptions
while invalidating guest TLB entries, since TLB invalidation is not
available so guest entries must be invalidated by setting them to unique
unmapped addresses, which could conflict with mappings set by the guest
or root if recently repartitioned.

Signed-off-by: James Hogan 
Cc: Paolo Bonzini 
Cc: "Radim Krčmář" 
Cc: Ralf Baechle 
Cc: David Daney 
Cc: Andreas Herrmann 
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org

KVM: MIPS/T&E: Report correct dcache line size

2017-03-28T14:36:18+00:00

Octeon CPUs don't report the correct dcache line size in CP0_Config1.DL,
so encode the correct value for the guest CP0_Config1.DL based on
cpu_dcache_line_size().

Signed-off-by: James Hogan 
Cc: Paolo Bonzini 
Cc: "Radim Krčmář" 
Cc: Ralf Baechle 
Cc: David Daney 
Cc: Andreas Herrmann 
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org

KVM: MIPS/TLB: Handle virtually tagged icaches

2017-03-28T14:36:17+00:00

When TLB entries are invalidated in the presence of a virtually tagged
icache, such as that found on Octeon CPUs, flush the icache so that we
don't get a reserved instruction exception even though the TLB mapping
is removed.

Signed-off-by: James Hogan 
Cc: Paolo Bonzini 
Cc: "Radim Krčmář" 
Cc: Ralf Baechle 
Cc: David Daney 
Cc: Andreas Herrmann 
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org

KVM: MIPS/Emulate: Adapt T&E CACHE emulation for Octeon

2017-03-28T14:36:17+00:00

Cache management is implemented separately for Cavium Octeon CPUs, so
r4k_blast_[id]cache aren't available. Instead for Octeon perform a local
icache flush using local_flush_icache_range(), and for other platforms
which don't use c-r4k.c use __flush_cache_all() / flush_icache_all().

Signed-off-by: James Hogan 
Cc: Paolo Bonzini 
Cc: "Radim Krčmář" 
Cc: Ralf Baechle 
Cc: David Daney 
Cc: Andreas Herrmann 
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org