linux.git/arch/mips/kernel, branch v2.6.29

MIPS: NEC VR5500 processor support fixup

2009-03-11T20:11:07+00:00

Current VR5500 processor support lacks of some functions which are
expected to be configured/synthesized on arch initialization.

Here're some VR5500A spec notes:

* All execution hazards are handled in hardware.

* Once VR5500A stops the operation of the pipeline by WAIT instruction,
  it could return from the standby mode only when either a reset, NMI
  request, or all enabled interrupts is/are detected.  In other words,
  if interrupts are disabled by Status.IE=0, it keeps in standby mode
  even when interrupts are internally asserted.

  Notes on WAIT: The operation of the processor is undefined if WAIT
  insn is in the branch delay slot.  The operation is also undefined
  if WAIT insn is executed when Status.EXL and Status.ERL are set to 1.

* VR5500A core only implements the Load prefetch.

With these changes, it boots fine.

Signed-off-by: Shinya Kuribayashi 
Signed-off-by: Ralf Baechle

MIPS: Fix build of non-CONFIG_SYSVIPC version of sys_32_ipc

2009-03-11T20:11:07+00:00

Signed-off-by: Xiaotian Feng 
Signed-off-by: Ralf Baechle

Revert "MIPS: Print irq handler description"

2009-02-27T17:56:35+00:00

This reverts commit 558d1de8ba9ebb1cc3f3062f1371b9330772164f.

MIPS: CVE-2009-0029: Enable syscall wrappers.

2009-02-27T17:56:35+00:00

Thanks to David Daney helping with debugging and testing.

Signed-off-by: Ralf Baechle 
Signed-off-by: David Daney

MIPS: Read watch registers with interrupts disabled.

2009-01-30T21:32:58+00:00

If a context switch occurred between the watch exception and reading the
watch registers, it would be possible for the new process to corrupt their
state.  Enabling interrupts only after the watch registers are read avoids
this race.

Signed-off-by: David Daney 
Signed-off-by: Ralf Baechle

MIPS: R2: Fix broken installation of cache error handler.

2009-01-30T21:32:58+00:00

Signed-off-by: Ralf Baechle

MIPS: SMTC: Fix build after recent creditial changes.

2009-01-30T21:32:56+00:00

Signed-off-by: Ralf Baechle

[CVE-2009-0029] Rename old_readdir to sys_old_readdir

2009-01-14T13:15:15+00:00

This way it matches the generic system call name convention.

Signed-off-by: Heiko Carstens

MIPS: Alchemy: RTC counter clocksource / clockevent support.

2009-01-11T09:57:27+00:00

Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent
device.  As a nice side effect, this also enables use of the 'wait'
instruction for runtime idle power savings.

If the counters aren't enabled/working properly, fall back on the
cp0 counter clock code.

Signed-off-by: Manuel Lauss 
Signed-off-by: Ralf Baechle

MIPS: make cp0 counter clocksource/event usable as fallback.

2009-01-11T09:57:26+00:00

The current mips clock build infrastructure lets a system only use
either the MIPS cp0 counter or a SoC specific timer as a clocksource /
clockevent device.

This patch renames the core cp0 counter clocksource / clockevent functions
from mips_* to r4k_* and updates the wrappers in asm-mips/time.h to
call these renamed functions instead.

Chips which can detect whether it is safe to use a chip-specific timer
can now fall back on the cp0 counter if necessary and possible
(e.g. Alchemy with a follow-on patch).

Existing behaviour is not changed in any way.

Signed-off-by: Manuel Lauss 
Signed-off-by: Ralf Baechle