linux.git/arch/mips/kernel/traps.c, branch v2.6.33

MIPS: Fixup of the r4k timer

2010-02-10T21:15:42+00:00

As reported by Maxime Bizon, the commit "MIPS: PowerTV: Fix support for
timer interrupts with > 64 external IRQs" have broken the r4k timer
since it didn't initialize the cp0_compare_irq_shift variable used in
c0_compare_int_pending() on the architectures whose cpu_has_mips_r2 is
false.

This patch fixes it via initializing the cp0_compare_irq_shift as the
cp0_compare_irq used in the old c0_compare_int_pending().

Reported-by: Maxime Bizon 
Signed-off-by: Wu Zhangjin 
Cc: David VomLehn 
Cc: mbizon@freebox.fr
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/922/
Tested-by: Shane McDonald 
Signed-off-by: Ralf Baechle

MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs

2010-01-27T23:03:31+00:00

The MIPS processor is limited to 64 external interrupt sources. Using a
greater number without IRQ sharing requires reading platform-specific
registers. On such platforms, reading the IntCtl register to determine
which interrupt corresponds to a timer interrupt will not work.

On MIPSR2 systems there is a solution - the TI bit in the Cause register,
specifically indicates that a timer interrupt has occured. This patch uses
that bit to detect interrupts for MIPSR2 processors, which may be expected
to work regardless of how the timer interrupt may be routed in the hardware.

Signed-off-by: David VomLehn (dvomlehn@cisco.com)
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/804/
Signed-off-by: Ralf Baechle

MIPS: Cleanup signal code initialization

2009-12-17T01:57:32+00:00

Signed-off-by: Ralf Baechle 
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/709/

MIPS: Modularize COP2 handling

2009-12-17T01:57:30+00:00

Away with the daemons of ifdef; get ready for future COP2 users.

Signed-off-by: Ralf Baechle 
Patchwork: http://patchwork.linux-mips.org/patch/708/

MIPS: Rewrite sysmips(MIPS_ATOMIC_SET, ...) in C with inline assembler

2009-09-17T18:07:49+00:00

This way it doesn't have to use CONFIG_CPU_HAS_LLSC anymore.

Signed-off-by: Ralf Baechle

MIPS: Move Cavium CP0 hwrena impl bits to cpu-feature-overrides.h

2009-06-17T10:06:31+00:00

We had an ugly #ifdef for Cavium Octeon hwrena bits in traps.c, remove
it to mach-cavium-octeon/cpu-feature-overrides.h

Signed-off-by: David Daney 
Signed-off-by: Ralf Baechle

MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.

2009-06-17T10:06:31+00:00

Some CPUs have implementation dependent rdhwr registers.  Allow them
to be enabled on a per CPU basis.

Signed-off-by: David Daney 
Signed-off-by: Ralf Baechle

MIPS: Use BUG_ON() where possible.

2009-03-30T12:49:44+00:00

Based on original patch by Stoyan Gaydarov  which
missed a few places.

Signed-off-by: Ralf Baechle

MIPS: R2: Fix problem with code that incorrectly modifies ebase.

2009-03-23T22:38:05+00:00

Commit 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e had a change that
incorrectly modified ebase. This backs out the lines that modified
ebase.
In addition, the ebase exception vector is now allocated with correct
alignment and the ebase register updated according to the architecture
specification.

Based on original patch by David VomLehn .

Signed-off-by: David VomLehn 
Signed-off-by: Chris Dearman 
Signed-off-by: Ralf Baechle

MIPS: Read watch registers with interrupts disabled.

2009-01-30T21:32:58+00:00

If a context switch occurred between the watch exception and reading the
watch registers, it would be possible for the new process to corrupt their
state.  Enabling interrupts only after the watch registers are read avoids
this race.

Signed-off-by: David Daney 
Signed-off-by: Ralf Baechle