linux.git/arch/mips/kernel/traps.c, branch v2.6.29

MIPS: Read watch registers with interrupts disabled.

2009-01-30T21:32:58+00:00

If a context switch occurred between the watch exception and reading the
watch registers, it would be possible for the new process to corrupt their
state.  Enabling interrupts only after the watch registers are read avoids
this race.

Signed-off-by: David Daney 
Signed-off-by: Ralf Baechle

MIPS: R2: Fix broken installation of cache error handler.

2009-01-30T21:32:58+00:00

Signed-off-by: Ralf Baechle

MIPS: For Cavium OCTEON set hwrena and lazily restore CP2 state.

2009-01-11T09:57:21+00:00

If on Cavium, be aware of cop2 and hwrena during do_cpu().

Signed-off-by: Tomaso Paoletti 
Signed-off-by: Paul Gortmaker 
Signed-off-by: David Daney 
Signed-off-by: Ralf Baechle

MIPS: Switch FPU emulator trap to BREAK instruction.

2008-10-30T14:44:34+00:00

Arguably using the address error handler has always been ugly.  But with
processors that handle unaligned loads and stores in hardware the
current mechanism ceases to work so switch it to a BREAK instruction and
allocate break code 514 to the FPU emulator.

Yoichi Yuasa provided a build fix for CONFIG_BUG=n.

Signed-off-by: Ralf Baechle 
Signed-off-by: Yoichi Yuasa

MIPS: Consider value of c0_ebase when computing value of exception base.

2008-10-30T14:44:33+00:00

It just so happens to be zero on all currently supported systems so this
hasn't bitten yet ...

[Ralf: Original patch from Cavium; handling of set_uncached_handler() and
de-ifdef'ed trap_init() implementation by me.]

Signed-off-by: Tomaso Paoletti 
Signed-off-by: David Daney 
Signed-off-by: Ralf Baechle

MIPS: Watch exception handling for HARDWARE_WATCHPOINTS.

2008-10-11T15:18:56+00:00

Here we hook up the watch exception handler so that it sends SIGTRAP when
the hardware watch registers are triggered.

Signed-off-by: David Daney 
Signed-off-by: Ralf Baechle

[MIPS] SMTC: Fix holes in SMTC and FPU affinity support.

2008-10-03T16:58:58+00:00

Signed-off-by: Kevin D. Kissell 
Signed-off-by: Ralf Baechle

[MIPS] Fix potential latency problem due to non-atomic cpu_wait.

2008-09-21T12:52:57+00:00

If an interrupt happened between checking of NEED_RESCHED and WAIT
instruction, adjust EPC to restart from checking of NEED_RESCHED.

Signed-off-by: Atsushi Nemoto 
Signed-off-by: Ralf Baechle

[MIPS] Fix WARNING: at kernel/smp.c:290

2008-09-05T20:24:11+00:00

trap_init issues flush_icache_range(), which uses ipi functions to
get icache flushing done on all cpus. But this is done before interrupts
are enabled and caused WARN_ON messages. This changeset introduces
a new local_flush_icache_range() and uses it before interrupts (and
additional CPUs) are enabled to avoid this problem.

Signed-off-by: Thomas Bogendoerfer 
Signed-off-by: Ralf Baechle

[MIPS] Fix data bus error recovery

2008-09-05T20:24:11+00:00

With -ffunction-section the entries in __dbe_table aren't no longer
sorted, so the lookup of exception addresses in do_be() failed for
some addresses. To avoid this we now sort __dbe_table.

Signed-off-by: Thomas Bogendoerfer 
Signed-off-by: Ralf Baechle