linux.git/arch/mips/kernel/pm-cps.c, branch v4.10

cpu/hotplug: Cleanup state names

2016-12-25T09:47:44+00:00

When the state names got added a script was used to add the extra argument
to the calls. The script basically converted the state constant to a
string, but the cleanup to convert these strings into meaningful ones did
not happen.

Replace all the useless strings with 'subsys/xxx/yyy:state' strings which
are used in all the other places already.

Signed-off-by: Thomas Gleixner 
Cc: Peter Zijlstra 
Cc: Sebastian Siewior 
Link: http://lkml.kernel.org/r/20161221192112.085444152@linutronix.de
Signed-off-by: Thomas Gleixner

MIPS: pm-cps: Generate idle state entry code when CPUs are onlined

2016-10-04T23:31:20+00:00

The MIPS Coherent Processing System (CPS) power management code has
previously generated code used to enter low power idle states once
during boot for all CPUs. This has the drawback that if a CPU is present
in the system but not being used (for example due to the maxcpus kernel
parameter) then we encounter problems due to not having probed that CPU
for information about its type & properties. The result of this is that
we generate entry code which is both unused, potentially entirely
invalid & likely to be unsuitable for the CPU in question anyway.

Avoid this by generating idle state entry code only when a CPU is
brought online. This way we only ever generate code for CPUs that we
know we've probed the properties of, and that will actually be used.

[ralf@linux-mips.org: Resolve merge conflict.]

Signed-off-by: Paul Burton 
Cc: Adam Buchbinder 
Cc: Masahiro Yamada 
Cc: Markos Chandras 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14259/
Signed-off-by: Ralf Baechle

MIPS: pm-cps: Support CM3 changes to Coherence Enable Register

2016-10-04T14:13:57+00:00

MIPS CM3 changed the management of coherence. Instead of a coherence
control register with a bitmask of coherent domains, CM3 simply has a
coherence enable register with a single bit to enable coherence of the
local core. Support this by clearing and setting this single bit to
disable / enable coherence.

Signed-off-by: Matt Redfearn 
Reviewed-by: Paul Burton 
Cc: Adam Buchbinder 
Cc: Tony Wu 
Cc: Masahiro Yamada 
Cc: Nikolay Martynov 
Cc: Kees Cook 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14226/
Signed-off-by: Ralf Baechle

MIPS: pm-cps: Add MIPSr6 CPU support

2016-10-04T14:13:57+00:00

This patch adds support for CPUs implementing the MIPSr6 ISA to the CPS
power management code. Three changes are necessary:

1. In MIPSr6, coupled coherence is necessary when CPUS implement multiple
   Virtual Processors (VPs).

2. MIPSr6 virtual processors are more like real cores and cannot yield
   to other VPs on the same core, so drop the MT ASE yield instruction.

3. To halt a MIPSr6 VP, the CPC VP_STOP register is used rather than the
   MT ASE TCHalt CP0 register.

Signed-off-by: Matt Redfearn 
Reviewed-by: Paul Burton 
Cc: Adam Buchbinder 
Cc: Masahiro Yamada 
Cc: Kees Cook 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14225/
Signed-off-by: Ralf Baechle

MIPS: pm-cps: Remove selection of sync types

2016-10-04T14:13:57+00:00

Instead of selecting an implementation or vendor specific sync type for
the required sync operations, always use the architecturally mandated
sync types which previous patches have put in place. The selection of
special sync types is now redundant an can be removed.

Signed-off-by: Matt Redfearn 
Reviewed-by: Paul Burton 
Cc: Adam Buchbinder 
Cc: Masahiro Yamada 
Cc: Kees Cook 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14223/
Signed-off-by: Ralf Baechle

MIPS: pm-cps: Use MIPS standard completion barrier

2016-10-04T14:13:57+00:00

SYNC type 0 is defined in the MIPS architecture as a completion barrier
where all loads/stores in the pipeline before the sync instruction must
complete before any loads/stores subsequent to the sync instruction.

In places where we require loads / stores be globally completed, use the
standard completion sync stype.

Signed-off-by: Matt Redfearn 
Reviewed-by: Paul Burton 
Cc: Adam Buchbinder 
Cc: Masahiro Yamada 
Cc: Andrew Morton 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14224/
Signed-off-by: Ralf Baechle

MIPS: pm-cps: Use MIPS standard lightweight ordering barrier

2016-10-04T14:13:57+00:00

Since R2 of the MIPS architecture, SYNC(0x10) has been an optional but
architecturally defined ordering barrier. If a CPU does not implement it,
the arch specifies that it must fall back to SYNC(0).

In places where we require that the instruction stream not be reordered,
but do not require that loads / stores are gloablly completed, use the
defined standard sync stype.

Signed-off-by: Matt Redfearn 
Reviewed-by: Paul Burton 
Cc: Adam Buchbinder 
Cc: Masahiro Yamada 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14221/
Signed-off-by: Ralf Baechle

MIPS: pm-cps: Update comments on barrier instructions

2016-10-04T14:13:57+00:00

This code makes large use of barriers, which had quite vague
descriptions. Update the comments to make the choice of barrier and
reason for it more clear.

Signed-off-by: Matt Redfearn 
Reviewed-by: Paul Burton 
Cc: Adam Buchbinder 
Cc: Masahiro Yamada 
Cc: Kees Cook 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14220/
Signed-off-by: Ralf Baechle

MIPS: pm-cps: Change FSB workaround to CPU blacklist

2016-10-04T14:13:57+00:00

The check for whether a CPU required the FSB flush workaround
previously required every CPU not requiring it to be whitelisted. That
approach does not scale well as new CPUs are introduced so change the
default from a WARN and returning an error to just returning 0. Any CPUs
requiring the workaround can then be added to the blacklist.

Signed-off-by: Matt Redfearn 
Reviewed-by: Paul Burton 
Cc: Adam Buchbinder 
Cc: Masahiro Yamada 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14218/
Signed-off-by: Ralf Baechle

tree-wide: replace config_enabled() with IS_ENABLED()

2016-08-04T12:50:07+00:00

The use of config_enabled() against config options is ambiguous.  In
practical terms, config_enabled() is equivalent to IS_BUILTIN(), but the
author might have used it for the meaning of IS_ENABLED().  Using
IS_ENABLED(), IS_BUILTIN(), IS_MODULE() etc.  makes the intention
clearer.

This commit replaces config_enabled() with IS_ENABLED() where possible.
This commit is only touching bool config options.

I noticed two cases where config_enabled() is used against a tristate
option:

 - config_enabled(CONFIG_HWMON)
  [ drivers/net/wireless/ath/ath10k/thermal.c ]

 - config_enabled(CONFIG_BACKLIGHT_CLASS_DEVICE)
  [ drivers/gpu/drm/gma500/opregion.c ]

I did not touch them because they should be converted to IS_BUILTIN()
in order to keep the logic, but I was not sure it was the authors'
intention.

Link: http://lkml.kernel.org/r/1465215656-20569-1-git-send-email-yamada.masahiro@socionext.com
Signed-off-by: Masahiro Yamada 
Acked-by: Kees Cook 
Cc: Stas Sergeev 
Cc: Matt Redfearn 
Cc: Joshua Kinard 
Cc: Jiri Slaby 
Cc: Bjorn Helgaas 
Cc: Borislav Petkov 
Cc: Markos Chandras 
Cc: "Dmitry V. Levin" 
Cc: yu-cheng yu 
Cc: James Hogan 
Cc: Brian Gerst 
Cc: Johannes Berg 
Cc: Peter Zijlstra 
Cc: Al Viro 
Cc: Will Drewry 
Cc: Nikolay Martynov 
Cc: Huacai Chen 
Cc: "H. Peter Anvin" 
Cc: Thomas Gleixner 
Cc: Daniel Borkmann 
Cc: Leonid Yegoshin 
Cc: Rafal Milecki 
Cc: James Cowgill 
Cc: Greg Kroah-Hartman 
Cc: Ralf Baechle 
Cc: Alex Smith 
Cc: Adam Buchbinder 
Cc: Qais Yousef 
Cc: Jiang Liu 
Cc: Mikko Rapeli 
Cc: Paul Gortmaker 
Cc: Denys Vlasenko 
Cc: Brian Norris 
Cc: Hidehiro Kawai 
Cc: "Luis R. Rodriguez" 
Cc: Andy Lutomirski 
Cc: Ingo Molnar 
Cc: Dave Hansen 
Cc: "Kirill A. Shutemov" 
Cc: Roland McGrath 
Cc: Paul Burton 
Cc: Kalle Valo 
Cc: Viresh Kumar 
Cc: Tony Wu 
Cc: Huaitong Han 
Cc: Sumit Semwal 
Cc: Alexei Starovoitov 
Cc: Juergen Gross 
Cc: Jason Cooper 
Cc: "David S. Miller" 
Cc: Oleg Nesterov 
Cc: Andrea Gelmini 
Cc: David Woodhouse 
Cc: Marc Zyngier 
Cc: Rabin Vincent 
Cc: "Maciej W. Rozycki" 
Cc: David Daney 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds