linux.git/arch/mips/kernel/cpu-probe.c, branch v4.3-rc2

MIPS: Advertise MSA support via HWCAP when present

2015-09-03T10:08:00+00:00

If MSA is supported by both the hardware & the kernel then advertise
that support to userland via the AT_HWCAP aux vector.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Guenter Roeck 
Cc: Matthew Fortune 
Cc: Leonid Yegoshin 
Cc: Maciej W. Rozycki 
Cc: linux-kernel@vger.kernel.org
Cc: Huacai Chen 
Cc: Markos Chandras 
Patchwork: https://patchwork.linux-mips.org/patch/10799/
Signed-off-by: Ralf Baechle

MIPS: Advertise MIPSr6 via HWCAP when appropriate

2015-09-03T10:07:59+00:00

When running on a CPU implementing the release 6 of the MIPS32 or MIPS64
ISA, advertise that to userland via the appropriate HWCAP bit.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Guenter Roeck 
Cc: Matthew Fortune 
Cc: Leonid Yegoshin 
Cc: Maciej W. Rozycki 
Cc: linux-kernel@vger.kernel.org
Cc: Huacai Chen 
Cc: Markos Chandras 
Patchwork: https://patchwork.linux-mips.org/patch/10798/
Signed-off-by: Ralf Baechle

MIPS: AT_HWCAP aux vector infrastructure

2015-09-03T10:07:59+00:00

In order for userland to determine whether various features are safe to
use, it will need to know both that the hardware supports those features
and that the kernel is recent enough & configured appropriately to
support them. For example under the O32 modeless FP proposal the dynamic
linker & ifunc resolvers will need this information.  The kernel is the
only thing in a position to know availability accurately, so the kernel
needs to provide the information to userland. This patch introduces the
infrastructure to provide the AT_HWCAP aux vector to userland in order
to provide that information. It also defines the 2 currently specified
flags, which indicate MIPSr6 & MSA support.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Guenter Roeck 
Cc: Matthew Fortune 
Cc: Kees Cook 
Cc: Huacai Chen 
Cc: Maciej W. Rozycki 
Cc: Alex Smith 
Cc: linux-kernel@vger.kernel.org
Cc: Leonid Yegoshin 
Cc: Markos Chandras 
Cc: Ingo Molnar 
Patchwork: https://patchwork.linux-mips.org/patch/10797/
Signed-off-by: Ralf Baechle

MIPS: Probe for small (1KiB) page support

2015-09-03T10:07:47+00:00

Probe Config3 for small page support. This will be useful to give clues
as to whether the PageGrain register exists.

Signed-off-by: James Hogan 
Cc: Maciej W. Rozycki 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10722/
Signed-off-by: Ralf Baechle

MIPS: Set up FTLB probability for I6400

2015-08-26T13:23:22+00:00

Set up the I6400 FTLB probability similar to P5600 and proAptiv.

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10652/
Signed-off-by: Ralf Baechle

MIPS: cpu-probe: Fix VTLB/FTLB configuration for R6

2015-08-26T13:23:21+00:00

R6 has dropped the MMUExtDef field from the config4 register and it
now returns 0. However, the return value means nothing in that case
and the only supported configuration for R6 is the VTLB+FTLB
(MMUextDef == 3). As a result, rework the code so that the correct
value is set for R6 cores.

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10651/
Signed-off-by: Ralf Baechle

MIPS: Add default case for the FTLB enable/disable code

2015-08-26T13:23:18+00:00

Add a default case for the FTLB enable/disable code. This will be used
to detect that something went wrong in the set_ftlb_enable() function
either because that function knows nothing about the running core, or
simply because the core can't turn its FTLB on/off.

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10650/
Signed-off-by: Ralf Baechle

MIPS: cpu-probe: Remove cp0 hazard barrier when enabling the FTLB

2015-08-26T13:23:17+00:00

We are so early in the boot process where we really don't want to
stall and wait for CP0 FTLB related changes become visible so just drop
the cp0 hazard barrier.

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10649/
Signed-off-by: Ralf Baechle

MIPS: Add MIPS I6400 probe support

2015-08-26T13:23:05+00:00

Add a case in cpu_probe_mips for the MIPS I6400 processor ID, which sets
the CPU type to the new CPU_I6400.

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10636/
Signed-off-by: Ralf Baechle

MIPS: R12000: Enable branch prediction global history

2015-06-21T19:54:13+00:00

The R12000 added a new feature to enhance branch prediction called
"global history".  Per the Vr10000 Series User Manual (U10278EJ4V0UM),
Coprocessor 0, Diagnostic Register (22):

"""
If bit 26 is set, branch prediction uses all eight bits of the global
history register.  If bit 26 is not set, then bits 25:23 specify a count
of the number of bits of global history to be used. Thus if bits 26:23
are all zero, global history is disabled.

The global history contains a record of the taken/not-taken status of
recently executed branches, and when used is XOR'ed with the PC of a
branch being predicted to produce a hashed value for indexing the BPT.
Some programs with small "working set of conditional branches" benefit
significantly from the use of such hashing, some see slight performance
degradation.
"""

This patch enables global history on R12000 CPUs and up by setting bit
26 in the branch prediction diagnostic register (CP0 $22) to '1'.  Bits
25:23 are left alone so that all eight bits of the global history
register are available for branch prediction.

Signed-off-by: Joshua Kinard 
Signed-off-by: Ralf Baechle