<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/arch/mips/kernel/cpu-probe.c, branch v3.9-rc2</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next</title>
<updated>2013-02-21T11:51:33+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2013-02-21T11:51:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=8bfc245f9ad7bd4e461179e4e7852ef99b8b6144'/>
<id>8bfc245f9ad7bd4e461179e4e7852ef99b8b6144</id>
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<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Probe for and report hardware virtualization support.</title>
<updated>2013-02-19T08:36:36+00:00</updated>
<author>
<name>David Daney</name>
<email>david.daney@cavium.com</email>
</author>
<published>2013-02-16T22:42:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=1e7decdb27ae89b2a0626635a8cf527f930bff1c'/>
<id>1e7decdb27ae89b2a0626635a8cf527f930bff1c</id>
<content type='text'>
The presence of the MIPS Virtualization Application-Specific Extension
is indicated by CP0_Config3[23].  Probe for this and report it in
/proc/cpuinfo.

Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
Patchwork: http://patchwork.linux-mips.org/patch/4904/
Signed-off-by: John Crispin &lt;blogic@openwrt.org&gt;
</content>
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<pre>
The presence of the MIPS Virtualization Application-Specific Extension
is indicated by CP0_Config3[23].  Probe for this and report it in
/proc/cpuinfo.

Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
Patchwork: http://patchwork.linux-mips.org/patch/4904/
Signed-off-by: John Crispin &lt;blogic@openwrt.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Add support for the M14KEc core.</title>
<updated>2013-02-16T23:15:23+00:00</updated>
<author>
<name>Steven J. Hill</name>
<email>sjhill@mips.com</email>
</author>
<published>2012-12-07T03:51:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=f8fa4811dbb264aef13f982e963389fd828b1ac0'/>
<id>f8fa4811dbb264aef13f982e963389fd828b1ac0</id>
<content type='text'>
Signed-off-by: Steven J. Hill &lt;sjhill@mips.com&gt;
Patchwork: http://patchwork.linux-mips.org/patch/4682/
Signed-off-by: John Crispin &lt;blogic@openwrt.org&gt;
</content>
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<pre>
Signed-off-by: Steven J. Hill &lt;sjhill@mips.com&gt;
Patchwork: http://patchwork.linux-mips.org/patch/4682/
Signed-off-by: John Crispin &lt;blogic@openwrt.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: show correct cpu name for 24KEc</title>
<updated>2013-02-16T23:15:16+00:00</updated>
<author>
<name>John Crispin</name>
<email>blogic@openwrt.org</email>
</author>
<published>2013-01-11T21:44:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=42f3caef039571df8c30a78a51c09cbdbaa7863b'/>
<id>42f3caef039571df8c30a78a51c09cbdbaa7863b</id>
<content type='text'>
Make sure 24KEc is properly identified inside /proc/cpuinfo

Signed-off-by: John Crispin &lt;blogic@openwrt.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Make sure 24KEc is properly identified inside /proc/cpuinfo

Signed-off-by: John Crispin &lt;blogic@openwrt.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Add printing of ISA version in cpuinfo.</title>
<updated>2013-02-15T22:07:38+00:00</updated>
<author>
<name>Steven J. Hill</name>
<email>sjhill@mips.com</email>
</author>
<published>2012-12-07T04:31:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=a96102be700f87283f168942cd09a2b30f86f324'/>
<id>a96102be700f87283f168942cd09a2b30f86f324</id>
<content type='text'>
Display the MIPS ISA version release in the /proc/cpuinfo file.

[ralf@linux-mips.org: Add support for MIPS I ... IV legacy architecture
revisions.  Also differenciate between MIPS32 and MIPS64 versions instead
of lumping them together as just r1 and r2.

Note to application programmers: this indicates the CPU's ISA level
It does not imply the current execution environment does support it.  For
example an O32 application seeing "mips64r2" would still be restricted by
by the execution environment to 32-bit - but the kernel could run mips64r2
code.  The same for a 32-bit kernel running on a 64-bit processor.  This
field doesn't include ASEs or optional architecture modules nor other
detailed flags such as the availability of an FPU.]

Signed-off-by: Steven J. Hill &lt;sjhill@mips.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/4714/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Display the MIPS ISA version release in the /proc/cpuinfo file.

[ralf@linux-mips.org: Add support for MIPS I ... IV legacy architecture
revisions.  Also differenciate between MIPS32 and MIPS64 versions instead
of lumping them together as just r1 and r2.

Note to application programmers: this indicates the CPU's ISA level
It does not imply the current execution environment does support it.  For
example an O32 application seeing "mips64r2" would still be restricted by
by the execution environment to 32-bit - but the kernel could run mips64r2
code.  The same for a 32-bit kernel running on a 64-bit processor.  This
field doesn't include ASEs or optional architecture modules nor other
detailed flags such as the availability of an FPU.]

Signed-off-by: Steven J. Hill &lt;sjhill@mips.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/4714/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Whitespace cleanup.</title>
<updated>2013-02-01T09:00:22+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2013-01-22T11:59:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=7034228792cc561e79ff8600f02884bd4c80e287'/>
<id>7034228792cc561e79ff8600f02884bd4c80e287</id>
<content type='text'>
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: R3000/R3081: Fix CPU detection.</title>
<updated>2012-12-05T18:58:54+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2012-06-08T06:10:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=2d33976fb395a5b9cb00f2c24132b3f272eb9a9d'/>
<id>2d33976fb395a5b9cb00f2c24132b3f272eb9a9d</id>
<content type='text'>
Broken since e05ea74fc56f347f872ef9946d27c53e8bf20864 (lmo) rsp.
cea7e2dfdef53fe55f359d00da562a268be06fd2 (kernel.org) [MIPS: Sort out CPU
type to name translation.]  These CPUs are no longer very popular to say
the least ...

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Reported-by: Murphy McCauley &lt;murphy.mccauley@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Broken since e05ea74fc56f347f872ef9946d27c53e8bf20864 (lmo) rsp.
cea7e2dfdef53fe55f359d00da562a268be06fd2 (kernel.org) [MIPS: Sort out CPU
type to name translation.]  These CPUs are no longer very popular to say
the least ...

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Reported-by: Murphy McCauley &lt;murphy.mccauley@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Add detection of DSP ASE Revision 2.</title>
<updated>2012-10-11T09:05:03+00:00</updated>
<author>
<name>Steven J. Hill</name>
<email>sjhill@mips.com</email>
</author>
<published>2012-08-03T15:26:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=ee80f7c73dc1b1f0ba9f82079c9bd1c0d1aedef8'/>
<id>ee80f7c73dc1b1f0ba9f82079c9bd1c0d1aedef8</id>
<content type='text'>
[ralf@linux-mips.org: This patch really only detects the ASE and passes its
existence on to userland via /proc/cpuinfo.  The DSP ASE Rev 2. adds new
resources but no resources that would need management by the kernel.]

Signed-off-by: Steven J. Hill &lt;sjhill@mips.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4165/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[ralf@linux-mips.org: This patch really only detects the ASE and passes its
existence on to userland via /proc/cpuinfo.  The DSP ASE Rev 2. adds new
resources but no resources that would need management by the kernel.]

Signed-off-by: Steven J. Hill &lt;sjhill@mips.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4165/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt)</title>
<updated>2012-10-11T09:04:34+00:00</updated>
<author>
<name>Al Cooper</name>
<email>alcooperx@gmail.com</email>
</author>
<published>2012-07-13T20:44:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=da4b62cd6762ce327f660c6e45c8d5a739197159'/>
<id>da4b62cd6762ce327f660c6e45c8d5a739197159</id>
<content type='text'>
The PCI (Program Counter Interrupt) bit in the "cause" register
is mandatory for MIPS32R2 cores, but has also been added to some R1
cores (BMIPS5000). This change adds a cpu feature bit to make it
easier to check for and use this feature.

Signed-off-by: Al Cooper &lt;alcooperx@gmail.com&gt;
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/4106/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The PCI (Program Counter Interrupt) bit in the "cause" register
is mandatory for MIPS32R2 cores, but has also been added to some R1
cores (BMIPS5000). This change adds a cpu feature bit to make it
easier to check for and use this feature.

Signed-off-by: Al Cooper &lt;alcooperx@gmail.com&gt;
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/4106/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'ralf-3.7' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next</title>
<updated>2012-09-28T14:29:55+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2012-09-28T14:29:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=cb418b34caddc970c1513e515aaa535246a4bba3'/>
<id>cb418b34caddc970c1513e515aaa535246a4bba3</id>
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</content>
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<pre>
</pre>
</div>
</content>
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