linux.git/arch/mips/kernel/cpu-probe.c, branch v3.14

MIPS: Netlogic: Identify XLP 9XX chip

2014-01-24T21:39:48+00:00

Adds processor ID of XLP 9XX to asm/cpu.h.  Update netlogic/xlp-hal/xlp.h
to add cpu_is_xlp9xx() and to update cpu_is_xlpii() to support XLP 9XX.

Signed-off-by: Jayachandran C 
Signed-off-by: John Crispin 
Patchwork: http://patchwork.linux-mips.org/patch/6274/

MIPS: kernel: cpu-probe: Add support for probing interAptiv cores

2014-01-22T19:19:01+00:00

Signed-off-by: Leonid Yegoshin 
Signed-off-by: Markos Chandras 
Signed-off-by: John Crispin 
Patchwork: http://patchwork.linux-mips.org/patch/6152/

MIPS: Add support for FTLBs

2014-01-22T19:19:00+00:00

The Fixed Page Size TLB (FTLB) is a set-associative dual entry TLB. Its
purpose is to reduce the number of TLB misses by increasing the effective
TLB size and keep the implementation complexity to minimum levels.
A supported core can have both VTLB and FTLB.

Reviewed-by: James Hogan 
Reviewed-by: Paul Burton 
Signed-off-by: Leonid Yegoshin 
Signed-off-by: Markos Chandras 
Signed-off-by: John Crispin 
Patchwork: http://patchwork.linux-mips.org/patch/6139/

MIPS: kernel: cpu-probe: Add support for probing proAptiv cores

2014-01-22T19:18:59+00:00

Signed-off-by: Leonid Yegoshin 
Signed-off-by: Markos Chandras 
Signed-off-by: John Crispin 
Patchwork: http://patchwork.linux-mips.org/patch/6135/

MIPS: features: Add initial support for Segmentation Control registers

2014-01-22T19:18:58+00:00

MIPS32R3 introduced a new set of Segmentation Control registers which
increase the flexibility of the segmented-based memory scheme.

Signed-off-by: Steven J. Hill 
Signed-off-by: Markos Chandras 
Signed-off-by: John Crispin 
Patchwork: http://patchwork.linux-mips.org/patch/6131/

MIPS: features: Add initial support for TLBINVF capable cores

2014-01-22T19:18:58+00:00

New Aptiv cores support the TLBINVF instruction for flushing
the VTLB.

Signed-off-by: Leonid Yegoshin 
Signed-off-by: Markos Chandras 
Signed-off-by: John Crispin 
Patchwork: http://patchwork.linux-mips.org/patch/6130/

MIPS: Support for 64-bit FP with O32 binaries

2014-01-13T22:40:56+00:00

CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs
do. In order to preserve backwards compatibility a 64-bit FPU will act
like a 32-bit FPU (by accessing doubles from the least significant 32
bits of an even-odd pair of FP registers) when the Status.FR bit is
zero, again just like a mips64 CPU. The standard O32 ABI is defined
expecting a 32-bit FPU, however recent toolchains support use of a
64-bit FPU from an O32 MIPS32 executable. When an ELF executable is
built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF
header.

With this patch the kernel will check the EF_MIPS_FP64 flag when
executing an O32 binary, and set Status.FR accordingly. The addition
of O32 64-bit FP support lessens the opportunity for optimisation in
the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is
introduced to allow this support to be disabled for those that don't
require it.

Inspired by an earlier patch by Leonid Yegoshin, but implemented more
cleanly & correctly.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/6154/
Signed-off-by: Ralf Baechle

MIPS: kernel: cpu-probe: Report CPU id during probe

2013-10-29T20:25:33+00:00

Signed-off-by: Leonid Yegoshin 
Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6023/
Signed-off-by: Ralf Baechle

MIPS: Tell R4k SC and MC variations apart

2013-10-29T20:24:48+00:00

There is no reliable way to tell R4000/R4400 SC and MC variations apart,
however simple heuristic should give good results.  Only the MC version
supports coherent caching so we can rely on such a mode having been set
for KSEG0 by the power-on firmware to reliably indicate an MC processor.
SC processors reportedly hang on coherent cached memory accesses and Linux
is linked to a cached load address so the firmware has to use the correct
caching mode to download the kernel image in a cached mode successfully.

OTOH if the firmware chooses to use either the non-coherent cached or the
uncached mode for KSEG0 on an MC processor, then the SC variant will be
reported, just as we currently do, so no regression here.

Signed-off-by: Maciej W. Rozycki 
Cc: Jonas Gorski 
Cc: MIPS Mailing List 
Patchwork: https://patchwork.linux-mips.org/patch/5882/
Signed-off-by: Ralf Baechle

MIPS: Disable usermode switching of the FR bit for MIPS R5 CPUs.

2013-09-19T09:23:10+00:00

Currently the kernel will always use the FR=0 register model for O32.  If
an O32 application did enable FR=1 mode, some data from another application
might be leaked in the extra registers becoming visible.

Iow, this patch is meant to make the kernel MIPS R5 tolerant but leaves
proper MIPS R5 support to a future patchset.

Signed-off-by: Ralf Baechle