linux.git/arch/mips/kernel/cpu-probe.c, branch v3.10

MIPS: Consolidate idle loop / WAIT instruction support in a single file.

2013-05-21T23:34:25+00:00

Signed-off-by: Ralf Baechle

MIPS: microMIPS: Add support for exception handling.

2013-05-09T15:55:18+00:00

All exceptions must be taken in microMIPS mode, never in classic
MIPS mode or the kernel falls apart. A few NOP instructions are
used to maintain the correct alignment of microMIPS versions of
the exception vectors.

Signed-off-by: Steven J. Hill

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

2013-04-05T19:23:12+00:00

Pull MIPS fixes from Ralf Baechle:
 "Fixes for a number of small glitches in various corners of the MIPS
  tree.  No particular areas is standing out.

  With this applied all MIPS defconfigs are building fine.  No merge
  conflicts are expected."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: Delete definition of SA_RESTORER.
  MIPS: Fix ISA level which causes secondary cache init bypassing and more
  MIPS: Fix build error cavium-octeon without CONFIG_SMP
  MIPS: Kconfig: Rename SNIPROM too
  MIPS: Alchemy: Fix typo "CONFIG_DEBUG_PCI"
  MIPS: Unbreak function tracer for 64-bit kernel.

MIPS: Fix ISA level which causes secondary cache init bypassing and more

2013-04-05T13:10:45+00:00

The commit a96102be70 introduced set_isa() where compatible ISA info is
also set aside from the one gets passed in. It means, for example, 1004K
will have MIPS_CPU_ISA_M32R2/M32R1/II/I flags. This leads to things like
the following inappropriate:

if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
    c->isa_level == MIPS_CPU_ISA_M32R2 ||
    c->isa_level == MIPS_CPU_ISA_M64R1 ||
    c->isa_level == MIPS_CPU_ISA_M64R2)

This patch fixes it.

Signed-off-by: Deng-Cheng Zhu 
Cc: Steven J. Hill 
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle

MIPS: VR4133: Fix probe for LL/SC.

2013-03-12T17:57:52+00:00

Signed-off-by: Yoichi Yuasa 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4963/
Signed-off-by: Ralf Baechle

Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next

2013-02-21T11:51:33+00:00

MIPS: Probe for and report hardware virtualization support.

2013-02-19T08:36:36+00:00

The presence of the MIPS Virtualization Application-Specific Extension
is indicated by CP0_Config3[23].  Probe for this and report it in
/proc/cpuinfo.

Signed-off-by: David Daney 
Patchwork: http://patchwork.linux-mips.org/patch/4904/
Signed-off-by: John Crispin

MIPS: Add support for the M14KEc core.

2013-02-16T23:15:23+00:00

Signed-off-by: Steven J. Hill 
Patchwork: http://patchwork.linux-mips.org/patch/4682/
Signed-off-by: John Crispin

MIPS: show correct cpu name for 24KEc

2013-02-16T23:15:16+00:00

Make sure 24KEc is properly identified inside /proc/cpuinfo

Signed-off-by: John Crispin

MIPS: Add printing of ISA version in cpuinfo.

2013-02-15T22:07:38+00:00

Display the MIPS ISA version release in the /proc/cpuinfo file.

[ralf@linux-mips.org: Add support for MIPS I ... IV legacy architecture
revisions.  Also differenciate between MIPS32 and MIPS64 versions instead
of lumping them together as just r1 and r2.

Note to application programmers: this indicates the CPU's ISA level
It does not imply the current execution environment does support it.  For
example an O32 application seeing "mips64r2" would still be restricted by
by the execution environment to 32-bit - but the kernel could run mips64r2
code.  The same for a 32-bit kernel running on a 64-bit processor.  This
field doesn't include ASEs or optional architecture modules nor other
detailed flags such as the availability of an FPU.]

Signed-off-by: Steven J. Hill 
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/4714/
Signed-off-by: Ralf Baechle