linux.git/arch/mips/kernel/cpu-probe.c, branch v2.6.29

MIPS: NEC VR5500 processor support fixup

2009-03-11T20:11:07+00:00

Current VR5500 processor support lacks of some functions which are
expected to be configured/synthesized on arch initialization.

Here're some VR5500A spec notes:

* All execution hazards are handled in hardware.

* Once VR5500A stops the operation of the pipeline by WAIT instruction,
  it could return from the standby mode only when either a reset, NMI
  request, or all enabled interrupts is/are detected.  In other words,
  if interrupts are disabled by Status.IE=0, it keeps in standby mode
  even when interrupts are internally asserted.

  Notes on WAIT: The operation of the processor is undefined if WAIT
  insn is in the branch delay slot.  The operation is also undefined
  if WAIT insn is executed when Status.EXL and Status.ERL are set to 1.

* VR5500A core only implements the Load prefetch.

With these changes, it boots fine.

Signed-off-by: Shinya Kuribayashi 
Signed-off-by: Ralf Baechle

MIPS: Alchemy: RTC counter clocksource / clockevent support.

2009-01-11T09:57:27+00:00

Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent
device.  As a nice side effect, this also enables use of the 'wait'
instruction for runtime idle power savings.

If the counters aren't enabled/working properly, fall back on the
cp0 counter clock code.

Signed-off-by: Manuel Lauss 
Signed-off-by: Ralf Baechle

MIPS: Add Cavium OCTEON processor constants and CPU probe.

2009-01-11T09:57:22+00:00

Add OCTEON constants to asm/cpu.h and asm/module.h.

Add probe function for Cavium OCTEON CPUs and hook it up.

Signed-off-by: Tomaso Paoletti 
Signed-off-by: David Daney 
Signed-off-by: Ralf Baechle

MIPS: Sort out CPU type to name translation.

2008-10-30T14:44:34+00:00

As noticed by David Daney , the old long switch
statement did not comply with the Linux C coding style.  It was also yet
another place of code to be changed when adding a new processor type
leading to annoying bugs for example in /proc/cpuinfo.

Fixed by moving the setting of the CPU type string into the core of the
probing code and a few BUG_ON() test to ensure the CPU probing code indeed
did its job and removing multiple now redundant tests.

Signed-off-by: Ralf Baechle

MIPS: Probe for watch registers on cores of all vendors, not just MTI.

2008-10-30T14:44:34+00:00

Signed-off-by: Ralf Baechle 
Acked-by: David Daney

MIPS: Probe watch registers and report configuration.

2008-10-11T15:18:56+00:00

Probe for watch register characteristics, and report them in /proc/cpuinfo.

Signed-off-by: David Daney 
Signed-off-by: Ralf Baechle

[MIPS] SMTC: Fix SMTC dyntick support.

2008-10-03T16:58:58+00:00

Rework of SMTC support to make it work with the new clock event system,
allowing "tickless" operation, and to make it compatible with the use of
the "wait_irqoff" idle loop.  The new clocking scheme means that the
previously optional IPI instant replay mechanism is now required, and has
been made more robust.

Signed-off-by: Kevin D. Kissell 
Signed-off-by: Ralf Baechle

[MIPS] Fix potential latency problem due to non-atomic cpu_wait.

2008-09-21T12:52:57+00:00

If an interrupt happened between checking of NEED_RESCHED and WAIT
instruction, adjust EPC to restart from checking of NEED_RESCHED.

Signed-off-by: Atsushi Nemoto 
Signed-off-by: Ralf Baechle

[MIPS] Move arch/mips/philips to arch/mips/nxp

2008-04-28T16:14:26+00:00

Signed-off-by: daniel.j.laird 
Signed-off-by: Ralf Baechle

[MIPS] Add support for MIPS CMP platform.

2008-04-28T16:14:26+00:00

Signed-off-by: Chris Dearman 
Signed-off-by: Atsushi Nemoto 
Signed-off-by: Ralf Baechle