linux.git/arch/mips/kernel/cpu-probe.c, branch v2.6.24

[MIPS] Fix shadow register support.

2007-11-15T23:21:49+00:00

Shadow register support would not possibly have worked on multicore
systems.  The support code for it was also depending not on MIPS R2 but
VSMP or SMTC kernels even though it makes perfect sense with UP kernels.

SR sets are a scarce resource and the expected usage pattern is that
users actually hardcode the register set numbers in their code.  So fix
the allocator by ditching it.  Move the remaining CPU probe bits into
the generic CPU probe.

Signed-off-by: Ralf Baechle

[MIPS] Add BUG_ON assertion for attempt to run kernel on the wrong CPU type.

2007-10-11T22:46:18+00:00

Signed-off-by: Ralf Baechle

[MIPS] Make facility to convert CPU types to strings generally available.

2007-10-11T22:46:17+00:00

So far /proc/cpuinfo has been the only user but human readable processor
name are more useful than that for proc.

Signed-off-by: Ralf Baechle

[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.

2007-10-11T22:46:05+00:00

It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.

Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.

Signed-off-by: Ralf Baechle

[MIPS] Add support for BCM47XX CPUs.

2007-10-11T22:46:02+00:00

Note that the BCM4710 does not support the wait instruction, this
is not a mistake in the code.

It originally comes from the OpenWrt patches.

Cc: Michael Buesch 
Cc: Felix Fietkau 
Cc: Florian Schirmer 
Signed-off-by: Aurelien Jarno 
Signed-off-by: Andrew Morton 
Signed-off-by: Ralf Baechle

[MIPS] 20Kc: Disable use of WAIT instruction.

2007-09-14T18:08:43+00:00

Another issue with 20Kc's WAIT, waiting for more details.  With the
2.6.23 release immindent simply disable the use of WAIT instead of a
more fancy workaround.

Signed-off-by: Ralf Baechle

[MIPS] Workaround for RM7000 WAIT instruction aka erratum 38

2007-07-20T17:57:39+00:00

Signed-off-by: Ralf Baechle

[MIPS] PMC MSP71xx mips common

2007-07-10T16:33:03+00:00

Patch to add mips common support for the PMC-Sierra MSP71xx devices.

Signed-off-by: Marc St-Jean 
Signed-off-by: Ralf Baechle

[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2

2007-07-10T16:33:02+00:00

Signed-off-by: Fuxin Zhang 
Signed-off-by: Ralf Baechle

[MIPS] Enable support for the userlocal hardware register

2007-07-10T16:33:02+00:00

Which will cut down the cost of RDHWR $29 which is used to obtain the
TLS pointer and so far being emulated in software down to a single cycle
operation.

Signed-off-by: Ralf Baechle