linux.git/arch/mips/kernel/asm-offsets.c, branch v3.11

MIPS: r4k,octeon,r2300: stack protector: change canary per task

2013-07-01T13:10:52+00:00

For non-SMP, uses the new random canary value that is stored in the
task struct whenever a new task is forked.  Based on ARM version in
df0698be14c6683606d5df2d83e3ae40f85ed0d9 and subject to the same
limitations: the variable GCC expects, __stack_chk_guard, is global,
so this will not work on SMP.

Quoting Nicolas Pitre : "One way to overcome this
GCC limitation would be to locate the __stack_chk_guard variable into
a memory page of its own for each CPU, and then use TLB locking to
have each CPU see its own page at the same virtual address for each of
them."

Signed-off-by: Gregory Fong 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5488/
Signed-off-by: Ralf Baechle

MIPS: ASM offsets for VCPU arch specific fields.

2013-05-08T01:55:37+00:00

Signed-off-by: Sanjay Lal 
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle

MIPS: Include PAGE_S{IZE,HIFT} in .

2012-12-28T16:04:10+00:00

Signed-off-by: Ralf Baechle

MIPS: Remove leftovers from the IRIX binary compat code.

2012-12-12T15:52:07+00:00

2957c9e61ee9c37e7ebf2c8acab03e073fe942fd (kernel.org) rsp.
b934da913f236bca00c41d9e386e980586000461 (lmo) [[MIPS] IRIX: Goodbye and
thanks for all the fish] left two fields in struct thread_struct which
were only being used for the IRIX compat code.  Remove them.

Signed-off-by: Ralf Baechle

MIPS: asm-offset.c: Delete unused irq_cpustat_t struct offsets.

2012-10-11T09:11:20+00:00

Originally added in 05b541489c48e7fbeec19a92acf8683230750d0a [Merge with
Linux 2.5.5.] over 10 years ago but never been used.

Signed-off-by: Ralf Baechle

MIPS: Remove unused task_struct.trap_no field.

2010-08-05T12:26:30+00:00

It is initialized to zero and only ever read.  Remove it, and pass zero in
its place.

Signed-off-by: David Daney 
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1531/
Signed-off-by: Ralf Baechle

MIPS: Two-level pagetables for 64-bit kernels with 64KB pages.

2010-02-27T11:53:03+00:00

For 64-bit kernels with 64KB pages and two level page tables, there are
42 bits worth of virtual address space This is larger than the 40 bits of
virtual address space obtained with the default 4KB Page size and three
levels, so there are no draw backs for using two level tables with this
configuration.

Signed-off-by: David Daney 
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/761/
Signed-off-by: Ralf Baechle

MIPS: Use PAGE_SIZE in assembly instead of _PAGE_SIZE.

2009-09-17T18:07:48+00:00

Now that PAGE_SIZE is available to assembly directly, there is no need
to separately expose it as _PAGE_SIZE through asm-offsets.

In addition, remove _PAGE_SHIFT from asm-offsets, since it was never
needed, and is not used anywhere.

Signed-off-by: Nelson Elhage 
Signed-off-by: Tim Abbott 
Signed-off-by: Ralf Baechle

MIPS: Add hibernation support

2009-06-17T10:06:31+00:00

[Ralf: SMP support requires CPU hotplugging which MIPS currently doesn't
support.  As implemented in this patch cache and tlb flushing will also be
invoked with interrupts disabled so smp_call_function() will blow up in
charming ways.  So limit to !SMP.]

Reviewed-by: Pavel Machek 
Reviewed-by: Yan Hua 
Reviewed-by: Arnaud Patard 
Reviewed-by: Atsushi Nemoto 
Signed-off-by: Wu Zhangjin 
Signed-off-by: Hu Hongbing 
Signed-off-by: Ralf Baechle

MIPS: Add Cavium OCTEON specific registers to ptrace.h and asm-offsets.c

2009-01-11T09:57:23+00:00

Signed-off-by: David Daney 
Signed-off-by: Tomaso Paoletti 
Signed-off-by: Ralf Baechle