linux.git/arch/mips/include/asm/system.h, branch v2.6.35

MIPS: New macro smp_mb__before_llsc.

2010-02-27T11:53:06+00:00

Replace some instances of smp_llsc_mb() with a new macro
smp_mb__before_llsc().  It is used before ll/sc sequences that are
documented as needing write barrier semantics.

The default implementation of smp_mb__before_llsc() is just smp_llsc_mb(),
so there are no changes in semantics.

Also simplify definition of smp_mb(), smp_rmb(), and smp_wmb() to be just
barrier() in the non-SMP case.

Signed-off-by: David Daney 
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/851/
Signed-off-by: Ralf Baechle

MIPS: Fix build error if __xchg() is not getting inlined.

2009-12-01T16:21:25+00:00

If __xchg() is not getting inlined the outline version of the function
will have a reference to __xchg_called_with_bad_pointer() which does not
exist remaining.  Fixed by using BUILD_BUG_ON() to check for allowable
operand sizes.

Signed-off-by: Ralf Baechle 
Patchwork: http://patchwork.linux-mips.org/patch/705/

MIPS: Allow kernel use of LL/SC to be separate from the presence of LL/SC.

2009-09-17T18:07:50+00:00

On some CPUs, it is more efficient to disable and enable interrupts in the
kernel rather than use ll/sc for atomic operations.  But if we were to set
cpu_has_llsc to false, we would break the userspace futex interface (in
asm/futex.h).

We separate the two concepts, with a new predicate kernel_uses_llsc, that
lets us disable the kernel's use of ll/sc while still allowing the futex
code to use it.

Also there were a couple of cases in bitops.h where we were using ll/sc
unconditionally even if cpu_has_llsc were false.

Signed-off-by: David Daney 
Signed-off-by: Ralf Baechle

MIPS: Rewrite clearing of ll_bit on context switch in C

2009-09-17T18:07:49+00:00

This also means there is now only one implementation not 3 left.

Signed-off-by: Ralf Baechle

MIPS: Rewrite sysmips(MIPS_ATOMIC_SET, ...) in C with inline assembler

2009-09-17T18:07:49+00:00

This way it doesn't have to use CONFIG_CPU_HAS_LLSC anymore.

Signed-off-by: Ralf Baechle

MIPS: Consolidate all CONFIG_CPU_HAS_LLSC use in a single C file.

2009-09-17T18:07:49+00:00

Signed-off-by: Ralf Baechle

MIPS: Scheduler support for HARDWARE_WATCHPOINTS.

2008-10-11T15:18:57+00:00

Here we hook up the scheduler.  Whenever we switch to a new process,
we check to see if the watch registers should be installed, and do it
if needed.

Signed-off-by: David Daney 
Signed-off-by: Ralf Baechle

MIPS: Move headfiles to new location below arch/mips/include

2008-10-11T15:18:52+00:00

Signed-off-by: Ralf Baechle