linux.git/arch/mips/include/asm/processor.h, branch v3.17

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

2014-08-07T15:47:00+00:00

Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for 3.17.  It contains:

   - misc Cavium Octeon, BCM47xx, BCM63xx and Alchemy  updates
   - MIPS ptrace updates and cleanups
   - various fixes that will also go to -stable
   - a number of cleanups and small non-critical fixes.
   - NUMA support for the Loongson 3.
   - more support for MSA
   - support for MAAR
   - various FP enhancements and fixes"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits)
  MIPS: jz4740: remove unnecessary null test before debugfs_remove
  MIPS: Octeon: remove unnecessary null test before debugfs_remove_recursive
  MIPS: ZBOOT: implement stack protector in compressed boot phase
  MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFT
  MIPS: Bonito64: remove a duplicate define
  MIPS: Malta: initialise MAARs
  MIPS: Initialise MAARs
  MIPS: detect presence of MAARs
  MIPS: define MAAR register accessors & bits
  MIPS: mark MSA experimental
  MIPS: Don't build MSA support unless it can be used
  MIPS: consistently clear MSA flags when starting & copying threads
  MIPS: 16 byte align MSA vector context
  MIPS: disable preemption whilst initialising MSA
  MIPS: ensure MSA gets disabled during boot
  MIPS: fix read_msa_* & write_msa_* functions on non-MSA toolchains
  MIPS: fix MSA context for tasks which don't use FP first
  MIPS: init upper 64b of vector registers when MSA is first used
  MIPS: save/disable MSA in lose_fpu
  MIPS: preserve scalar FP CSR when switching vector context
  ...

MIPS: 16 byte align MSA vector context

2014-08-01T22:06:44+00:00

The MSA specification upon first read appears to suggest that it is safe
to perform vector loads & stores with arbitrary alignment. However it
leaves provision for "address-dependent exceptions"... Align the vector
context to a 16 byte boundary to ensure that the kernel cannot cause any
such exceptions.

Note that the fpu field of struct thread_struct was already at a 16 byte
boundary within the struct, the introduction of FPU_ALIGN simply makes
the requirement explicit. The only part of this impacting the generated
kernel binary is ARCH_MIN_TASKALIGN.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7308/
Signed-off-by: Ralf Baechle

arch, locking: Ciao arch_mutex_cpu_relax()

2014-07-17T10:32:47+00:00

The arch_mutex_cpu_relax() function, introduced by 34b133f, is
hacky and ugly. It was added a few years ago to address the fact
that common cpu_relax() calls include yielding on s390, and thus
impact the optimistic spinning functionality of mutexes. Nowadays
we use this function well beyond mutexes: rwsem, qrwlock, mcs and
lockref. Since the macro that defines the call is in the mutex header,
any users must include mutex.h and the naming is misleading as well.

This patch (i) renames the call to cpu_relax_lowlatency  ("relax, but
only if you can do it with very low latency") and (ii) defines it in
each arch's asm/processor.h local header, just like for regular cpu_relax
functions. On all archs, except s390, cpu_relax_lowlatency is simply cpu_relax,
and thus we can take it out of mutex.h. While this can seem redundant,
I believe it is a good choice as it allows us to move out arch specific
logic from generic locking primitives and enables future(?) archs to
transparently define it, similarly to System Z.

Signed-off-by: Davidlohr Bueso 
Signed-off-by: Peter Zijlstra 
Cc: Andrew Morton 
Cc: Anton Blanchard 
Cc: Aurelien Jacquiot 
Cc: Benjamin Herrenschmidt 
Cc: Bharat Bhushan 
Cc: Catalin Marinas 
Cc: Chen Liqin 
Cc: Chris Metcalf 
Cc: Christian Borntraeger 
Cc: Chris Zankel 
Cc: David Howells 
Cc: David S. Miller 
Cc: Deepthi Dharwar 
Cc: Dominik Dingel 
Cc: Fenghua Yu 
Cc: Geert Uytterhoeven 
Cc: Guan Xuetao 
Cc: Haavard Skinnemoen 
Cc: Hans-Christian Egtvedt 
Cc: Heiko Carstens 
Cc: Helge Deller 
Cc: Hirokazu Takata 
Cc: Ivan Kokshaysky 
Cc: James E.J. Bottomley 
Cc: James Hogan 
Cc: Jason Wang 
Cc: Jesper Nilsson 
Cc: Joe Perches 
Cc: Jonas Bonn 
Cc: Joseph Myers 
Cc: Kees Cook 
Cc: Koichi Yasutake 
Cc: Lennox Wu 
Cc: Linus Torvalds 
Cc: Mark Salter 
Cc: Martin Schwidefsky 
Cc: Matt Turner 
Cc: Max Filippov 
Cc: Michael Neuling 
Cc: Michal Simek 
Cc: Mikael Starvik 
Cc: Nicolas Pitre 
Cc: Paolo Bonzini 
Cc: Paul Burton 
Cc: Paul E. McKenney 
Cc: Paul Gortmaker 
Cc: Paul Mackerras 
Cc: Qais Yousef 
Cc: Qiaowei Ren 
Cc: Rafael Wysocki 
Cc: Ralf Baechle 
Cc: Richard Henderson 
Cc: Richard Kuo 
Cc: Russell King 
Cc: Steven Miao 
Cc: Steven Rostedt 
Cc: Stratos Karafotis 
Cc: Tim Chen 
Cc: Tony Luck 
Cc: Vasily Kulikov 
Cc: Vineet Gupta 
Cc: Vineet Gupta 
Cc: Waiman Long 
Cc: Will Deacon 
Cc: Wolfram Sang 
Cc: adi-buildroot-devel@lists.sourceforge.net
Cc: linux390@de.ibm.com
Cc: linux-alpha@vger.kernel.org
Cc: linux-am33-list@redhat.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-c6x-dev@linux-c6x.org
Cc: linux-cris-kernel@axis.com
Cc: linux-hexagon@vger.kernel.org
Cc: linux-ia64@vger.kernel.org
Cc: linux@lists.openrisc.net
Cc: linux-m32r-ja@ml.linux-m32r.org
Cc: linux-m32r@ml.linux-m32r.org
Cc: linux-m68k@lists.linux-m68k.org
Cc: linux-metag@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-parisc@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-s390@vger.kernel.org
Cc: linux-sh@vger.kernel.org
Cc: linux-xtensa@linux-xtensa.org
Cc: sparclinux@vger.kernel.org
Link: http://lkml.kernel.org/r/1404079773.2619.4.camel@buesod1.americas.hpqcorp.net
Signed-off-by: Ingo Molnar

MIPS: Basic MSA context switching support

2014-03-26T22:09:10+00:00

This patch adds support for context switching the MSA vector registers.
These 128 bit vector registers are aliased with the FP registers - an
FP register accesses the least significant bits of the vector register
with which it is aliased (ie. the register with the same index). Due to
both this & the requirement that the scalar FPU must be 64-bit (FR=1) if
enabled at the same time as MSA the kernel will enable MSA & scalar FP
at the same time for tasks which use MSA. If we restore the MSA vector
context then we might as well enable the scalar FPU since the reason it
was left disabled was to allow for lazy FP context restoring - but we
just restored the FP context as it's a subset of the vector context. If
we restore the FP context and have previously used MSA then we have to
restore the whole vector context anyway (see comment in
enable_restore_fp_context for details) so similarly we might as well
enable MSA.

Thus if a task does not use MSA then it will continue to behave as
without this patch - the scalar FP context will be saved & restored as
usual. But if a task executes an MSA instruction then it will save &
restore the vector context forever more.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6431/
Signed-off-by: Ralf Baechle

MIPS: Update outdated comment

2014-03-26T22:09:09+00:00

The hard-coded offsets mentioned in this comment seem to not exist
anymore, so remove mention of them from the comment.

Signed-off-by: Paul Burton 
Reviewed-by: Qais Yousef 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6421/
Signed-off-by: Ralf Baechle

MIPS: Simplify FP context access

2014-03-26T22:09:09+00:00

This patch replaces the fpureg_t typedef with a "union fpureg" enabling
easier access to 32 & 64 bit values. This allows the access macros used
in cp1emu.c to be simplified somewhat. It will also make it easier to
expand the width of the FP registers as will be done in a future
patch in order to support the 128 bit registers introduced with MSA.

No behavioural change is intended by this patch.

Signed-off-by: Paul Burton 
Reviewed-by: Qais Yousef 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6532/
Signed-off-by: Ralf Baechle

MIPS: Cleanup indentation and whitespace

2013-07-01T13:10:57+00:00

Signed-off-by: Tony Wu 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5536/
Signed-off-by: Ralf Baechle

MIPS: Netlogic: COP2 save/restore code

2013-06-13T15:46:41+00:00

Add COP2 register state structure and functions for Netlogic XLP. The
RX and TX buffers and status registers are to be saved. Since the
registers are 64-bit, do the implementation in inline assembly which
works on both 32-bit and 64-bit kernels.

Signed-off-by: Jayachandran C 
Cc: linux-mips@linux-mips.org
Cc: ddaney.cavm@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/5413/
Signed-off-by: Ralf Baechle

MIPS: Move cop2 save/restore to switch_to()

2013-06-13T15:46:41+00:00

Move the common code for saving and restoring platform specific COP2
registers to switch_to(). This will make supporting new platforms (like
Netlogic XLP) easier.

The platform specific COP2 definitions are to be specified in
asm/processor.h and in asm/cop2.h.

Signed-off-by: Jayachandran C 
Cc: linux-mips@linux-mips.org
Cc: ddaney.cavm@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/5411/
Signed-off-by: Ralf Baechle

MIPS: Idle: Consolidate all declarations in .

2013-05-21T23:34:27+00:00

Signed-off-by: Ralf Baechle