linux.git/arch/mips/include/asm/pgtable-bits.h, branch v5.1

MIPS: Allow RIXI to be used on non-R2 or R6 cores

2016-05-13T13:30:25+00:00

Some processors, like Broadcom's BMIPS4380 and BMIPS5000 support RIXI and the
"rotr" instruction, which can be used to get a slightly more efficient page
table layout.

Introduce a CONFIG_CPU_HAS_RIXI such that those cores can benefit from this
feature. Perform the conditional check updates where relevant.

Signed-off-by: Florian Fainelli 
Cc: john@phrozen.org
Cc: cernekee@gmail.com
Cc: jon.fraser@broadcom.com
Cc: pgynther@google.com
Cc: paul.burton@imgtec.com
Cc: ddaney.cavm@gmail.com
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12505/
Signed-off-by: Ralf Baechle

MIPS: mm: Fix MIPS32 36b physical addressing (alchemy, netlogic)

2016-05-13T13:30:25+00:00

There are 2 distinct cases in which a kernel for a MIPS32 CPU
(CONFIG_CPU_MIPS32=y) may use 64 bit physical addresses
(CONFIG_PHYS_ADDR_T_64BIT=y):

  - 36 bit physical addressing as used by RMI Alchemy & Netlogic XLP/XLR
    CPUs.

  - MIPS32r5 eXtended Physical Addressing (XPA).

These 2 cases are distinct in that they require different behaviour from
the kernel - the EntryLo registers have different formats. Until Linux
v4.1 we only supported the first case, with code conditional upon the 2
aforementioned Kconfig variables being set. Commit c5b367835cfc ("MIPS:
Add support for XPA.") added support for the second case, but did so by
modifying the code that existed for the first case rather than treating
the 2 cases as distinct. Since the EntryLo registers have different
formats this breaks the 36 bit Alchemy/XLP/XLR case. Fix this by
splitting the 2 cases, with XPA cases now being conditional upon
CONFIG_XPA and the non-XPA case matching the code as it existed prior to
commit c5b367835cfc ("MIPS: Add support for XPA.").

Signed-off-by: Paul Burton 
Reported-by: Manuel Lauss 
Tested-by: Manuel Lauss 
Fixes: c5b367835cfc ("MIPS: Add support for XPA.")
Cc: James Hogan 
Cc: David Daney 
Cc: Huacai Chen 
Cc: Maciej W. Rozycki 
Cc: Paul Gortmaker 
Cc: Aneesh Kumar K.V 
Cc: Peter Zijlstra (Intel) 
Cc: David Hildenbrand 
Cc: Andrew Morton 
Cc: Ingo Molnar 
Cc: Alex Smith 
Cc: Kirill A. Shutemov 
Cc: stable@vger.kernel.org # v4.1+
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13119/
Signed-off-by: Ralf Baechle

MIPS: mm: Standardise on _PAGE_NO_READ, drop _PAGE_READ

2016-05-13T13:30:25+00:00

Ever since support for RI/XI was implemented by commit 6dd9344cfc41
("MIPS: Implement Read Inhibit/eXecute Inhibit") we've had a mixture of
_PAGE_READ & _PAGE_NO_READ bits. Rather than keep both around, switch
away from using _PAGE_READ to determine page presence & instead invert
the use to _PAGE_NO_READ. Wherever we formerly had no definition for
_PAGE_NO_READ, change what was _PAGE_READ to _PAGE_NO_READ. The end
result is that we consistently use _PAGE_NO_READ to determine whether a
page is readable, regardless of whether RI/XI is implemented.

Signed-off-by: Paul Burton 
Reviewed-by: James Hogan 
Cc: David Daney 
Cc: Huacai Chen 
Cc: Maciej W. Rozycki 
Cc: Paul Gortmaker 
Cc: Aneesh Kumar K.V 
Cc: Andrew Morton 
Cc: Alex Smith 
Cc: Kirill A. Shutemov 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13116/
Signed-off-by: Ralf Baechle

MIPS: Use enums to make asm/pgtable-bits.h readable

2016-05-13T13:30:25+00:00

asm/pgtable-bits.h has grown to become an unreadable mess of #ifdef
directives defining bits conditionally upon other bits all at the
preprocessing stage, for no good reason.

Instead of having quite so many #ifdef's, simply use enums to provide
sequential numbering for bit shifts, without having to keep track
manually of what the last bit defined was. Masks are defined separately,
after the shifts, which allows for most of their definitions to be
reused for all systems rather than duplicated.

This patch is not intended to make any behavioural change to the code -
all bits should be used in the same way they were before this patch.

Signed-off-by: Paul Burton 
Reviewed-by: James Hogan 
Cc: Maciej W. Rozycki 
Cc: Alex Smith 
Cc: Kirill A. Shutemov 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13115/
Signed-off-by: Ralf Baechle

MIPS: Remove redundant asm/pgtable-bits.h inclusions

2016-05-13T13:30:25+00:00

asm/pgtable-bits.h is included in 2 assembly files and thus has to
ifdef around C code, however nothing defined by the header is used
in either of the assembly files that include it.

Remove the redundant inclusions such that asm/pgtable-bits.h doesn't
need to #ifdef around C code, for cleanliness and in preparation for
later patches which will add more C.

Signed-off-by: Paul Burton 
Reviewed-by: James Hogan 
Cc: Maciej W. Rozycki 
Cc: Jonas Gorski 
Cc: Alex Smith 
Cc: Kirill A. Shutemov 
Cc: Andrew Morton 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13114/
Signed-off-by: Ralf Baechle

mips, thp: remove infrastructure for handling splitting PMDs

2016-01-16T01:56:32+00:00

With new refcounting we don't need to mark PMDs splitting.  Let's drop
code to handle this.

pmdp_splitting_flush() is not needed too: on splitting PMD we will do
pmdp_clear_flush() + set_pte_at().  pmdp_clear_flush() will do IPI as
needed for fast_gup.

Signed-off-by: Kirill A. Shutemov 
Cc: Sasha Levin 
Cc: Aneesh Kumar K.V 
Cc: Jerome Marchand 
Cc: Vlastimil Babka 
Cc: Andrea Arcangeli 
Cc: Hugh Dickins 
Cc: Dave Hansen 
Cc: Mel Gorman 
Cc: Rik van Riel 
Cc: Naoya Horiguchi 
Cc: Steve Capper 
Cc: Johannes Weiner 
Cc: Michal Hocko 
Cc: Christoph Lameter 
Cc: David Rientjes 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

Merge branch '4.2-fixes' into mips-for-linux-next

2015-09-03T12:06:33+00:00

MIPS: Use Ingenic-specific write combine attribute on all Ingenic platforms

2015-09-03T10:08:01+00:00

The Ingenic-specific write combining cache attribute was defined based
on CONFIG_MACH_JZ4740 and therefore not used on JZ4780. Change this to
CONFIG_MACH_INGENIC so that it gets used on all Ingenic platforms.

Signed-off-by: Alex Smith 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10769/
Signed-off-by: Ralf Baechle

MIPS: pgtable-bits.h: Correct _PAGE_GLOBAL_SHIFT build failure

2015-08-30T11:16:40+00:00

Correct a build failure introduced by be0c37c9 [MIPS: Rearrange PTE bits
into fixed positions.]:

In file included from ./arch/mips/include/asm/io.h:27:0,
                 from ./arch/mips/include/asm/page.h:176,
                 from include/linux/mm_types.h:15,
                 from include/linux/sched.h:27,
                 from include/linux/ptrace.h:5,
                 from arch/mips/kernel/cpu-probe.c:16:
./arch/mips/include/asm/pgtable-bits.h:164:0: error: "_PAGE_GLOBAL_SHIFT" redefined [-Werror]
 #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
 ^
./arch/mips/include/asm/pgtable-bits.h:141:0: note: this is the location of the previous definition
 #define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
 ^
cc1: all warnings being treated as errors
make[2]: *** [arch/mips/kernel/cpu-probe.o] Error 1

for 64BIT/CPU_MIPSR1/MIPS_HUGE_TLB_SUPPORT configurations.  Remove the
scattered double `_PAGE_NO_EXEC_SHIFT' and `_PAGE_GLOBAL_SHIFT' macro
definitions and rearrange them so that the respective macros these
definitions are based on are also those used for guarding conditionals.

[ralf@linux-mips.org: resolved conflicts and updated commments.]

Signed-off-by: Maciej W. Rozycki 
Cc: Steven J. Hill 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9960/
Signed-off-by: Ralf Baechle

MIPS: pgtable-bits: Fix XPA damage to R6 definitions.

2015-06-09T08:45:05+00:00

Commit be0c37c985ed ("MIPS: Rearrange PTE bits into fixed positions.")
rearranged the PTE bits into fixed positions in preparation for the XPA
support. However, this patch broke R6 since it only took R2 cores
into consideration for the RI/XI bits leading to boot failures. We fix
this by adding the missing CONFIG_CPU_MIPSR6 definitions

Fixes: be0c37c985ed ("MIPS: Rearrange PTE bits into fixed positions.")
Cc: Steven J. Hill 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10208/
Signed-off-by: Markos Chandras 
Signed-off-by: Ralf Baechle