linux.git/arch/mips/include/asm/pgtable-bits.h, branch v3.14 Linux kernel source tree MIPS: Whitespace cleanup. 2013-02-01T09:00:22+00:00 Ralf Baechle ralf@linux-mips.org 2013-01-22T11:59:30+00:00 7034228792cc561e79ff8600f02884bd4c80e287 Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Nuke trailing whitespace. 2013-02-01T09:00:21+00:00 Ralf Baechle ralf@linux-mips.org 2013-01-18T15:58:26+00:00 82de378caad24b066ce8f9d9743c8fa96ad01f82 Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: PMC-Sierra Yosemite: Remove support. 2012-12-13T17:15:30+00:00 Ralf Baechle ralf@linux-mips.org 2012-12-11T20:02:55+00:00 bdf20507da11a9a5b32ef04fa09f352828189aef Nobody seems to be interested anymore and upstream also never had an ethernet driver. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Nobody seems to be interested anymore and upstream also never had an
ethernet driver.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Transparent Huge Pages support 2012-12-12T15:48:52+00:00 Ralf Baechle ralf@linux-mips.org 2012-10-18T11:54:15+00:00 970d032fec3f9687446595ee2569fb70b858a69f Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Control huge tlb support via Kconfig symbol MIPS_HUGE_TLB_SUPPORT 2012-12-12T15:48:47+00:00 David Daney david.daney@cavium.com 2012-10-16T22:48:10+00:00 aa1762f49c81a14d0453e4f67f922e4f155510a3 We need Huge TLBs for HUGETLB_PAGE, or the soon to follow TRANSPARENT_HUGEPAGE. collect this information under a single Kconfig symbol. Signed-off-by: David Daney <david.daney@cavium.com> 
We need Huge TLBs for HUGETLB_PAGE, or the soon to follow
TRANSPARENT_HUGEPAGE.  collect this information under a single Kconfig
symbol.

Signed-off-by: David Daney <david.daney@cavium.com>
MIPS: tlbex: Better debug output. 2012-11-26T12:41:06+00:00 Ralf Baechle ralf@linux-mips.org 2012-10-16T20:20:26+00:00 a2c763e0747f28c7b2eb4c5058344790bfee0ed9 Pgtable bits are assigned dynamically depending on processor feature and statically based on kernel configuration. To make sense out of the disassembled TLB exception handlers a list of the actual assignments used for a particular configuration and hardware setup can be very useful. Output the actual TLB exception handlers in a format that simplifies their post processsing from dmesg output. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Pgtable bits are assigned dynamically depending on processor feature and
statically based on kernel configuration.  To make sense out of the
disassembled TLB exception handlers a list of the actual assignments
used for a particular configuration and hardware setup can be very useful.

Output the actual TLB exception handlers in a format that simplifies their
post processsing from dmesg output.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'. 2012-09-13T22:00:34+00:00 Steven J. Hill sjhill@mips.com 2012-09-13T21:51:46+00:00 05857c64ecf897209c16ffad9bb3e8d359dd5dca Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files and use new 'cpu_has_rixi' instead. Signed-off-by: Steven J. Hill <sjhill@mips.com> Acked-by: David Daney <david.daney@cavium.com> 
Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files
and use new 'cpu_has_rixi' instead.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Acked-by: David Daney <david.daney@cavium.com>
MIPS: Implement Read Inhibit/eXecute Inhibit 2010-02-27T11:53:26+00:00 David Daney ddaney@caviumnetworks.com 2010-02-10T23:12:47+00:00 6dd9344cfc41bcc60a01cdc828cb278be7a10e01 The SmartMIPS ASE specifies how Read Inhibit (RI) and eXecute Inhibit (XI) bits in the page tables work. The upper two bits of EntryLo{0,1} are RI and XI when the feature is enabled in the PageGrain register. SmartMIPS only covers 32-bit systems. Cavium Octeon+ extends this to 64-bit systems by continuing to place the RI and XI bits in the top of EntryLo even when EntryLo is 64-bits wide. Because we need to carry the RI and XI bits in the PTE, the layout of the PTE is changed. There is a two instruction overhead in the TLB refill hot path to get the EntryLo bits into the proper position. Also the TLB load exception has to probe the TLB to check if RI or XI caused the exception. Also of note is that the layout of the PTE bits is done at compile and runtime rather than statically. In the 32-bit case this allows for the same number of PFN bits as before the patch as the _PAGE_HUGE is not supported in 32-bit kernels (we have _PAGE_NO_EXEC and _PAGE_NO_READ instead of _PAGE_READ and _PAGE_HUGE). The patch is tested on Cavium Octeon+, but should also work on 32-bit systems with the Smart-MIPS ASE. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/952/ Patchwork: http://patchwork.linux-mips.org/patch/956/ Patchwork: http://patchwork.linux-mips.org/patch/962/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
The SmartMIPS ASE specifies how Read Inhibit (RI) and eXecute Inhibit
(XI) bits in the page tables work.  The upper two bits of EntryLo{0,1}
are RI and XI when the feature is enabled in the PageGrain register.
SmartMIPS only covers 32-bit systems.  Cavium Octeon+ extends this to
64-bit systems by continuing to place the RI and XI bits in the top of
EntryLo even when EntryLo is 64-bits wide.

Because we need to carry the RI and XI bits in the PTE, the layout of
the PTE is changed.  There is a two instruction overhead in the TLB
refill hot path to get the EntryLo bits into the proper position.
Also the TLB load exception has to probe the TLB to check if RI or XI
caused the exception.

Also of note is that the layout of the PTE bits is done at compile and
runtime rather than statically.  In the 32-bit case this allows for
the same number of PFN bits as before the patch as the _PAGE_HUGE is
not supported in 32-bit kernels (we have _PAGE_NO_EXEC and
_PAGE_NO_READ instead of _PAGE_READ and _PAGE_HUGE).

The patch is tested on Cavium Octeon+, but should also work on 32-bit
systems with the Smart-MIPS ASE.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/952/
Patchwork: http://patchwork.linux-mips.org/patch/956/
Patchwork: http://patchwork.linux-mips.org/patch/962/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Add hugetlbfs page defines. 2009-06-17T10:06:30+00:00 David Daney ddaney@caviumnetworks.com 2009-05-28T00:47:43+00:00 dd7943920b492d9d8a79080fe05e25ecd7e10bc3 Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Move headfiles to new location below arch/mips/include 2008-10-11T15:18:52+00:00 Ralf Baechle ralf@linux-mips.org 2008-09-16T17:48:51+00:00 384740dc49ea651ba350704d13ff6be9976e37fe Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>