linux.git/arch/mips/include/asm/cpu-features.h, branch v5.6 Linux kernel source tree MIPS: Add MAC2008 Support 2020-01-22T23:56:08+00:00 Jiaxun Yang jiaxun.yang@flygoat.com 2020-01-13T10:16:11+00:00 ece276de2a1f90b6a7836d388c372b9025345469 MAC2008 means the processor implemented IEEE754 style Fused MADD instruction. It was introduced in Release3 but removed in Release5. The toolchain support of MAC2008 have never landed except for Loongson processors. This patch aimed to disabled the MAC2008 if it's optional. For MAC2008 only processors, we corrected math-emu behavior to align with actual hardware behavior. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> [paulburton@kernel.org: Fixup MIPSr2-r5 check in cpu_set_fpu_2008.] Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: linux-mips@vger.kernel.org Cc: chenhc@lemote.com Cc: paul.burton@mips.com Cc: linux-kernel@vger.kernel.org 
MAC2008 means the processor implemented IEEE754 style Fused MADD
instruction. It was introduced in Release3 but removed in Release5.

The toolchain support of MAC2008 have never landed except for Loongson
processors.

This patch aimed to disabled the MAC2008 if it's optional. For
MAC2008 only processors, we corrected math-emu behavior to align
with actual hardware behavior.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
[paulburton@kernel.org: Fixup MIPSr2-r5 check in cpu_set_fpu_2008.]
Signed-off-by: Paul Burton <paulburton@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: chenhc@lemote.com
Cc: paul.burton@mips.com
Cc: linux-kernel@vger.kernel.org
MIPS: tlbex: Remove cpu_has_local_ebase 2019-09-03T13:20:54+00:00 Paul Burton paul.burton@mips.com 2019-08-31T15:40:46+00:00 775b089aeffa98d5f69045d9dc4fe3aaba1bc9e1 The cpu_has_local_ebase macro is, confusingly, not used to indicate whether the EBase register is local to a CPU or not. Instead it indicates whether we want to generate the TLB refill exception vector each time a CPU is brought online. Doing this makes little sense on any system, since we always use the same value for EBase & thus we cannot have different TLB refill exception handlers per CPU. Regenerating the code is not only pointless but also can be actively harmful, as commit 8759934e2b6b ("MIPS: Build uasm-generated code only once to avoid CPU Hotplug problem") described. That commit introduced cpu_has_local_ebase to disable the handler regeneration for Loongson machines, but this is by no means a Loongson-specific problem. Remove cpu_has_local_ebase & simply generate the TLB refill handler once during boot, just like the rest of the TLB exception handlers. Signed-off-by: Paul Burton <paul.burton@mips.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: linux-mips@vger.kernel.org 
The cpu_has_local_ebase macro is, confusingly, not used to indicate
whether the EBase register is local to a CPU or not. Instead it
indicates whether we want to generate the TLB refill exception vector
each time a CPU is brought online. Doing this makes little sense on any
system, since we always use the same value for EBase & thus we cannot
have different TLB refill exception handlers per CPU.

Regenerating the code is not only pointless but also can be actively
harmful, as commit 8759934e2b6b ("MIPS: Build uasm-generated code only
once to avoid CPU Hotplug problem") described. That commit introduced
cpu_has_local_ebase to disable the handler regeneration for Loongson
machines, but this is by no means a Loongson-specific problem.

Remove cpu_has_local_ebase & simply generate the TLB refill handler once
during boot, just like the rest of the TLB exception handlers.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: linux-mips@vger.kernel.org
MIPS: Treat Loongson Extensions as ASEs 2019-08-26T10:42:40+00:00 Jiaxun Yang jiaxun.yang@flygoat.com 2019-05-29T08:42:59+00:00 d2f965549006acb865c4638f1f030ebcefdc71f6 Recently, binutils had split Loongson-3 Extensions into four ASEs: MMI, CAM, EXT, EXT2. This patch do the samething in kernel and expose them in cpuinfo so applications can probe supported ASEs at runtime. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Yunqiang Su <ysu@wavecomp.com> Cc: stable@vger.kernel.org # v4.14+ Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org 
Recently, binutils had split Loongson-3 Extensions into four ASEs:
MMI, CAM, EXT, EXT2. This patch do the samething in kernel and expose
them in cpuinfo so applications can probe supported ASEs at runtime.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Yunqiang Su <ysu@wavecomp.com>
Cc: stable@vger.kernel.org # v4.14+
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
MIPS: MemoryMapID (MMID) Support 2019-02-04T18:56:41+00:00 Paul Burton paul.burton@mips.com 2019-02-02T01:43:28+00:00 c8790d657b0a8d42801fb4536f6f106b4b6306e8 Introduce support for using MemoryMapIDs (MMIDs) as an alternative to Address Space IDs (ASIDs). The major difference between the two is that MMIDs are global - ie. an MMID uniquely identifies an address space across all coherent CPUs. In contrast ASIDs are non-global per-CPU IDs, wherein each address space is allocated a separate ASID for each CPU upon which it is used. This global namespace allows a new GINVT instruction be used to globally invalidate TLB entries associated with a particular MMID across all coherent CPUs in the system, removing the need for IPIs to invalidate entries with separate ASIDs on each CPU. The allocation scheme used here is largely borrowed from arm64 (see arch/arm64/mm/context.c). In essence we maintain a bitmap to track available MMIDs, and MMIDs in active use at the time of a rollover to a new MMID version are preserved in the new version. The allocation scheme requires efficient 64 bit atomics in order to perform reasonably, so this support depends upon CONFIG_GENERIC_ATOMIC64=n (ie. currently it will only be included in MIPS64 kernels). The first, and currently only, available CPU with support for MMIDs is the MIPS I6500. This CPU supports 16 bit MMIDs, and so for now we cap our MMIDs to 16 bits wide in order to prevent the bitmap growing to absurd sizes if any future CPU does implement 32 bit MMIDs as the architecture manuals suggest is recommended. When MMIDs are in use we also make use of GINVT instruction which is available due to the global nature of MMIDs. By executing a sequence of GINVT & SYNC 0x14 instructions we can avoid the overhead of an IPI to each remote CPU in many cases. One complication is that GINVT will invalidate wired entries (in all cases apart from type 0, which targets the entire TLB). In order to avoid GINVT invalidating any wired TLB entries we set up, we make sure to create those entries using a reserved MMID (0) that we never associate with any address space. Also of note is that KVM will require further work in order to support MMIDs & GINVT, since KVM is involved in allocating IDs for guests & in configuring the MMU. That work is not part of this patch, so for now when MMIDs are in use KVM is disabled. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org 
Introduce support for using MemoryMapIDs (MMIDs) as an alternative to
Address Space IDs (ASIDs). The major difference between the two is that
MMIDs are global - ie. an MMID uniquely identifies an address space
across all coherent CPUs. In contrast ASIDs are non-global per-CPU IDs,
wherein each address space is allocated a separate ASID for each CPU
upon which it is used. This global namespace allows a new GINVT
instruction be used to globally invalidate TLB entries associated with a
particular MMID across all coherent CPUs in the system, removing the
need for IPIs to invalidate entries with separate ASIDs on each CPU.

The allocation scheme used here is largely borrowed from arm64 (see
arch/arm64/mm/context.c). In essence we maintain a bitmap to track
available MMIDs, and MMIDs in active use at the time of a rollover to a
new MMID version are preserved in the new version. The allocation scheme
requires efficient 64 bit atomics in order to perform reasonably, so
this support depends upon CONFIG_GENERIC_ATOMIC64=n (ie. currently it
will only be included in MIPS64 kernels).

The first, and currently only, available CPU with support for MMIDs is
the MIPS I6500. This CPU supports 16 bit MMIDs, and so for now we cap
our MMIDs to 16 bits wide in order to prevent the bitmap growing to
absurd sizes if any future CPU does implement 32 bit MMIDs as the
architecture manuals suggest is recommended.

When MMIDs are in use we also make use of GINVT instruction which is
available due to the global nature of MMIDs. By executing a sequence of
GINVT & SYNC 0x14 instructions we can avoid the overhead of an IPI to
each remote CPU in many cases. One complication is that GINVT will
invalidate wired entries (in all cases apart from type 0, which targets
the entire TLB). In order to avoid GINVT invalidating any wired TLB
entries we set up, we make sure to create those entries using a reserved
MMID (0) that we never associate with any address space.

Also of note is that KVM will require further work in order to support
MMIDs & GINVT, since KVM is involved in allocating IDs for guests & in
configuring the MMU. That work is not part of this patch, so for now
when MMIDs are in use KVM is disabled.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
MIPS: Hardcode cpu_has_mips* where target ISA allows 2018-11-27T06:49:20+00:00 Paul Burton paul.burton@mips.com 2018-11-26T18:58:40+00:00 1aeba347b3a90a8b22f1c3eed0dcfba38bb8dbb8 In the same vein as commit 93e01942a6eb ("MIPS: Hardcode cpu_has_* where known at compile time due to ISA"), we can use our knowledge of the ISA being targeted by the kernel build to make cpu_has_mips* macros compile-time constant in some cases. This allows the compiler greater opportunity to optimize out code which will never execute. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21245/ Cc: linux-mips@linux-mips.org 
In the same vein as commit 93e01942a6eb ("MIPS: Hardcode cpu_has_* where
known at compile time due to ISA"), we can use our knowledge of the ISA
being targeted by the kernel build to make cpu_has_mips* macros
compile-time constant in some cases. This allows the compiler greater
opportunity to optimize out code which will never execute.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/21245/
Cc: linux-mips@linux-mips.org
MIPS: Use Kconfig to select CPU_NO_EFFICIENT_FFS 2018-11-12T22:26:16+00:00 Paul Burton paul.burton@mips.com 2018-11-08T23:44:55+00:00 57eeacede4db235891ddc37544262413f909763e Select CONFIG_CPU_NO_EFFICIENT_FFS via Kconfig when the kernel is configured for a pre-MIPS32r1 CPU, rather than defining its equivalent in asm/cpu-features.h based upon overrides of cpu_has_mips* macros. The latter only works if a platform has an cpu-feature-overrides.h header which defines cpu_has_mips* macros, which are not generally needed. There are many cases where we know that the target ISA for a kernel build is MIPS32r1 or later & thus includes the CLZ instruction, without requiring any overrides from the platform. Using Kconfig allows us to take those into account, and more naturally make a decision about instruction support using information about the target ISA. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21045/ Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Zhaoxiu Zeng <zhaoxiu.zeng@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org 
Select CONFIG_CPU_NO_EFFICIENT_FFS via Kconfig when the kernel is
configured for a pre-MIPS32r1 CPU, rather than defining its equivalent
in asm/cpu-features.h based upon overrides of cpu_has_mips* macros.

The latter only works if a platform has an cpu-feature-overrides.h
header which defines cpu_has_mips* macros, which are not generally
needed. There are many cases where we know that the target ISA for a
kernel build is MIPS32r1 or later & thus includes the CLZ instruction,
without requiring any overrides from the platform. Using Kconfig allows
us to take those into account, and more naturally make a decision about
instruction support using information about the target ISA.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/21045/
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Zhaoxiu Zeng <zhaoxiu.zeng@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
MIPS: Hardcode cpu_has_fpu=0 when CONFIG_MIPS_FP_SUPPORT=n 2018-11-09T18:23:15+00:00 Paul Burton paul.burton@mips.com 2018-11-07T23:14:03+00:00 b372e83b67eb296d85654e2dde8a0e6105083b16 When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point, so there's no point in detecting presence of an FPU. Hardcode cpu_has_fpu=0 such that we optimize out code that makes use of the FPU. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21005/ Cc: linux-mips@linux-mips.org 
When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point, so
there's no point in detecting presence of an FPU. Hardcode
cpu_has_fpu=0 such that we optimize out code that makes use of the FPU.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/21005/
Cc: linux-mips@linux-mips.org
MIPS: Hardcode cpu_has_mmips=1 for microMIPS kernels 2018-11-08T18:23:38+00:00 Paul Burton paul.burton@mips.com 2018-11-07T23:19:41+00:00 a013ba392843b2f65088f198a7125a78d48c6533 If we built the kernel targeting the microMIPS ISA then the very fact that the kernel is running implies that the CPU supports microMIPS. Thus we can hardcode cpu_has_mmips to 1 allowing the compiler greater scope for optimisation due to the compile-time constant. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21022/ Cc: linux-mips@linux-mips.org 
If we built the kernel targeting the microMIPS ISA then the very fact
that the kernel is running implies that the CPU supports microMIPS. Thus
we can hardcode cpu_has_mmips to 1 allowing the compiler greater scope
for optimisation due to the compile-time constant.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/21022/
Cc: linux-mips@linux-mips.org
MIPS: Hardcode cpu_has_* where known at compile time due to ISA 2018-07-24T21:09:13+00:00 Paul Burton paul.burton@mips.com 2017-06-12T18:54:23+00:00 93e01942a6eb1ce730b42158d0d6c6531fe29ca0 Many architectural features have over time moved from being optional to either be required or removed by newer architecture releases. This means that in many cases we can know at compile time whether a feature will be supported or not purely due to the knowledge we have about the ISA the kernel build is targeting. This patch introduces a bunch of utility macros for checking for supported options, ASEs & combinations of those with ISA revisions. It then makes use of these in the default definitions of cpu_has_* macros. The result is that many of the macros become compile-time constant, allowing more optimisation opportunities for the compiler - particularly with kernels built for later ISA revisions. To demonstrate the effect of this patch, the following table shows the size in bytes of the kernel binary as reported by scripts/bloat-o-meter for v4.12-rc4 maltasmvp_defconfig kernels with & without this patch. A variant of maltasmvp_defconfig with CONFIG_CPU_MIPS32_R6 selected is also shown, to demonstrate that MIPSr6 systems benefit more due to extra features becoming required by that architecture revision. Builds of pistachio_defconfig are also shown, as although this is a MIPSr2 platform it doesn't hardcode any features in a machine-specific cpu-feature-overrides.h, which allows it to gain more from this patch than the equivalent Malta r2 build. Config | Before | After | Change ----------------|---------|---------|--------- maltasmvp | 7248316 | 7247714 | -602 maltasmvp + r6 | 6955595 | 6950777 | -4818 pistachio | 8650977 | 8363898 | -287079 Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/16360/ Cc: Joshua Kinard <kumba@gentoo.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org 
Many architectural features have over time moved from being optional to
either be required or removed by newer architecture releases. This means
that in many cases we can know at compile time whether a feature will be
supported or not purely due to the knowledge we have about the ISA the
kernel build is targeting.

This patch introduces a bunch of utility macros for checking for
supported options, ASEs & combinations of those with ISA revisions. It
then makes use of these in the default definitions of cpu_has_* macros.
The result is that many of the macros become compile-time constant,
allowing more optimisation opportunities for the compiler - particularly
with kernels built for later ISA revisions.

To demonstrate the effect of this patch, the following table shows the
size in bytes of the kernel binary as reported by scripts/bloat-o-meter
for v4.12-rc4 maltasmvp_defconfig kernels with & without this patch. A
variant of maltasmvp_defconfig with CONFIG_CPU_MIPS32_R6 selected is
also shown, to demonstrate that MIPSr6 systems benefit more due to extra
features becoming required by that architecture revision. Builds of
pistachio_defconfig are also shown, as although this is a MIPSr2
platform it doesn't hardcode any features in a machine-specific
cpu-feature-overrides.h, which allows it to gain more from this patch
than the equivalent Malta r2 build.

     Config         | Before  | After   |  Change
    ----------------|---------|---------|---------
     maltasmvp      | 7248316 | 7247714 |    -602
     maltasmvp + r6 | 6955595 | 6950777 |   -4818
     pistachio      | 8650977 | 8363898 | -287079

Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/16360/
Cc: Joshua Kinard <kumba@gentoo.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
MIPS: perf: More robustly probe for the presence of per-tc counters 2018-05-15T14:16:16+00:00 Matt Redfearn matt.redfearn@mips.com 2018-04-20T10:23:04+00:00 800fb71281ca2ed5c8a7299e10ebc0de2f61cdda The presence of per TC performance counters is now detected by cpu-probe.c and indicated by MIPS_CPU_MT_PER_TC_PERF_COUNTERS in cpu_data. Switch detection of the feature to use this new flag rather than blindly testing the implementation specific config7 register with a magic number. Signed-off-by: Matt Redfearn <matt.redfearn@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Maciej W. Rozycki <macro@mips.com> Cc: Paul Burton <paul.burton@mips.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Robert Richter <rric@kernel.org> Cc: linux-mips@linux-mips.org Cc: oprofile-list@lists.sf.net Patchwork: https://patchwork.linux-mips.org/patch/19142/ Signed-off-by: James Hogan <jhogan@kernel.org> 
The presence of per TC performance counters is now detected by
cpu-probe.c and indicated by MIPS_CPU_MT_PER_TC_PERF_COUNTERS in
cpu_data. Switch detection of the feature to use this new flag rather
than blindly testing the implementation specific config7 register with a
magic number.

Signed-off-by: Matt Redfearn <matt.redfearn@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Maciej W. Rozycki <macro@mips.com>
Cc: Paul Burton <paul.burton@mips.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Robert Richter <rric@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: oprofile-list@lists.sf.net
Patchwork: https://patchwork.linux-mips.org/patch/19142/
Signed-off-by: James Hogan <jhogan@kernel.org>