linux.git/arch/mips/include/asm/cpu-features.h, branch v2.6.32 Linux kernel source tree MIPS: Allow kernel use of LL/SC to be separate from the presence of LL/SC. 2009-09-17T18:07:50+00:00 David Daney ddaney@caviumnetworks.com 2009-07-13T18:15:19+00:00 b791d1193af9772040e592d5aa161790f800b762 On some CPUs, it is more efficient to disable and enable interrupts in the kernel rather than use ll/sc for atomic operations. But if we were to set cpu_has_llsc to false, we would break the userspace futex interface (in asm/futex.h). We separate the two concepts, with a new predicate kernel_uses_llsc, that lets us disable the kernel's use of ll/sc while still allowing the futex code to use it. Also there were a couple of cases in bitops.h where we were using ll/sc unconditionally even if cpu_has_llsc were false. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
On some CPUs, it is more efficient to disable and enable interrupts in the
kernel rather than use ll/sc for atomic operations.  But if we were to set
cpu_has_llsc to false, we would break the userspace futex interface (in
asm/futex.h).

We separate the two concepts, with a new predicate kernel_uses_llsc, that
lets us disable the kernel's use of ll/sc while still allowing the futex
code to use it.

Also there were a couple of cases in bitops.h where we were using ll/sc
unconditionally even if cpu_has_llsc were false.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Allow CPU specific overriding of CP0 hwrena impl bits. 2009-06-17T10:06:31+00:00 David Daney ddaney@caviumnetworks.com 2009-05-13T22:59:55+00:00 fbeda19f82aa07082d2e1607a9f5114141dae2ac Some CPUs have implementation dependent rdhwr registers. Allow them to be enabled on a per CPU basis. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Some CPUs have implementation dependent rdhwr registers.  Allow them
to be enabled on a per CPU basis.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions. 2009-06-17T10:06:26+00:00 David Daney ddaney@caviumnetworks.com 2009-05-12T19:41:53+00:00 41f0e4d041aa30507a34998c29d0b7ac0bede277 Some CPUs do not need ehb instructions after writing CP0 registers. By allowing ehb generation to be overridden in cpu-feature-overrides.h, we can save a few instructions in the TLB handler hot paths. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Some CPUs do not need ehb instructions after writing CP0 registers.
By allowing ehb generation to be overridden in
cpu-feature-overrides.h, we can save a few instructions in the TLB
handler hot paths.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Enable CLO / CLZ instructions via separate CPU property 2009-05-14T12:50:26+00:00 Ralf Baechle ralf@linux-mips.org 2009-04-19T01:21:22+00:00 47740eb887796608fb4c629aa6b8507a2fb6c0eb This is useful for IDT RC32332, RC32334 and NEC VR5500 processors which do not implement the full MIPS32 / MIPS64 architecture. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
This is useful for IDT RC32332, RC32334 and NEC VR5500 processors which do
not implement the full MIPS32 / MIPS64 architecture.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Hook Cavium OCTEON cache init into cache.c 2009-01-11T09:57:22+00:00 David Daney ddaney@caviumnetworks.com 2008-12-11T23:33:27+00:00 47d979eca33f8df49bfead2d5efa23a70b413882 Follow precedent of other boards, and hook-up the CPU specific cache init. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Follow precedent of other boards, and hook-up the CPU specific cache
init.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: New feature test macro cpu_has_mips_r 2008-10-30T14:44:33+00:00 Ralf Baechle ralf@linux-mips.org 2008-10-28T09:37:47+00:00 c46b302b948e2070cb713171207c42e9586f131a cpu_has_mips_r is true if a processor is MIPS32 or MIPS64, any architecture revision. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
cpu_has_mips_r is true if a processor is MIPS32 or MIPS64, any architecture
revision.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Move headfiles to new location below arch/mips/include 2008-10-11T15:18:52+00:00 Ralf Baechle ralf@linux-mips.org 2008-09-16T17:48:51+00:00 384740dc49ea651ba350704d13ff6be9976e37fe Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>