linux.git/arch/mips/include/asm/bitops.h, branch v5.6

MIPS: bitops: Use smp_mb__before_atomic in test_* ops

2019-10-07T16:42:58+00:00

Use smp_mb__before_atomic() rather than smp_mb__before_llsc() in
test_and_set_bit(), test_and_clear_bit() & test_and_change_bit(). The
_atomic() versions make semantic sense in these cases, and will allow a
later patch to omit redundant barriers for Loongson3 systems that
already include a barrier within __test_bit_op().

Signed-off-by: Paul Burton 
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen 
Cc: Jiaxun Yang 
Cc: linux-kernel@vger.kernel.org

MIPS: bitops: Emit Loongson3 sync workarounds within asm

2019-10-07T16:42:57+00:00

Generate the sync instructions required to workaround Loongson3 LL/SC
errata within inline asm blocks, which feels a little safer than doing
it from C where strictly speaking the compiler would be well within its
rights to insert a memory access between the separate asm statements we
previously had, containing sync & ll instructions respectively.

Signed-off-by: Paul Burton 
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen 
Cc: Jiaxun Yang 
Cc: linux-kernel@vger.kernel.org

MIPS: bitops: Use BIT_WORD() & BITS_PER_LONG

2019-10-07T16:42:55+00:00

Rather than using custom SZLONG_LOG & SZLONG_MASK macros to shift & mask
a bit index to form word & bit offsets respectively, make use of the
standard BIT_WORD() & BITS_PER_LONG macros for the same purpose.

volatile is added to the definition of pointers to the long-sized word
we'll operate on, in order to prevent the compiler complaining that we
cast away the volatile qualifier of the addr argument. This should have
no effect on generated code, which in the LL/SC case is inline asm
anyway & in the non-LLSC case access is constrained by compiler barriers
provided by raw_local_irq_{save,restore}().

Signed-off-by: Paul Burton 
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen 
Cc: Jiaxun Yang 
Cc: linux-kernel@vger.kernel.org

MIPS: bitops: Abstract LL/SC loops

2019-10-07T16:42:53+00:00

Introduce __bit_op() & __test_bit_op() macros which abstract away the
implementation of LL/SC loops. This cuts down on a lot of duplicate
boilerplate code, and also allows R10000_LLSC_WAR to be handled outside
of the individual bitop functions.

Signed-off-by: Paul Burton 
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen 
Cc: Jiaxun Yang 
Cc: linux-kernel@vger.kernel.org

MIPS: bitops: Avoid redundant zero-comparison for non-LLSC

2019-10-07T16:42:52+00:00

The IRQ-disabling non-LLSC fallbacks for bitops on UP systems already
return a zero or one, so there's no need to perform another comparison
against zero. Move these comparisons into the LLSC paths to avoid the
redundant work.

Signed-off-by: Paul Burton 
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen 
Cc: Jiaxun Yang 
Cc: linux-kernel@vger.kernel.org

MIPS: bitops: Use the BIT() macro

2019-10-07T16:42:50+00:00

Use the BIT() macro in asm/bitops.h rather than open-coding its
equivalent.

Signed-off-by: Paul Burton 
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen 
Cc: Jiaxun Yang 
Cc: linux-kernel@vger.kernel.org

MIPS: bitops: Allow immediates in test_and_{set,clear,change}_bit

2019-10-07T16:42:49+00:00

The logical operations or & xor used in the test_and_set_bit_lock(),
test_and_clear_bit() & test_and_change_bit() functions currently force
the value 1<
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen 
Cc: Jiaxun Yang 
Cc: linux-kernel@vger.kernel.org

MIPS: bitops: Implement test_and_set_bit() in terms of _lock variant

2019-10-07T16:42:47+00:00

The only difference between test_and_set_bit() & test_and_set_bit_lock()
is memory ordering barrier semantics - the former provides a full
barrier whilst the latter only provides acquire semantics.

We can therefore implement test_and_set_bit() in terms of
test_and_set_bit_lock() with the addition of the extra memory barrier.
Do this in order to avoid duplicating logic.

Signed-off-by: Paul Burton 
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen 
Cc: Jiaxun Yang 
Cc: linux-kernel@vger.kernel.org

MIPS: bitops: ins start position is always an immediate

2019-10-07T16:42:42+00:00

The start position for an ins instruction is always encoded as an
immediate, so allowing registers to be used by the inline asm makes no
sense. It should never happen anyway since a bit index should always be
small enough to be treated as an immediate, but remove the nonsensical
"r" for sanity.

Signed-off-by: Paul Burton 
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen 
Cc: Jiaxun Yang 
Cc: linux-kernel@vger.kernel.org

MIPS: bitops: Use MIPS_ISA_REV, not #ifdefs

2019-10-07T16:42:41+00:00

Rather than #ifdef on CONFIG_CPU_* to determine whether the ins
instruction is supported we can simply check MIPS_ISA_REV to discover
whether we're targeting MIPSr2 or higher. Do so in order to clean up the
code.

Signed-off-by: Paul Burton 
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen 
Cc: Jiaxun Yang 
Cc: linux-kernel@vger.kernel.org