linux.git/arch/mips/boot, branch v4.19

kbuild: rename LDFLAGS to KBUILD_LDFLAGS

2018-08-23T23:22:08+00:00

Commit a0f97e06a43c ("kbuild: enable 'make CFLAGS=...' to add
additional options to CC") renamed CFLAGS to KBUILD_CFLAGS.

Commit 222d394d30e7 ("kbuild: enable 'make AFLAGS=...' to add
additional options to AS") renamed AFLAGS to KBUILD_AFLAGS.

Commit 06c5040cdb13 ("kbuild: enable 'make CPPFLAGS=...' to add
additional options to CPP") renamed CPPFLAGS to KBUILD_CPPFLAGS.

For some reason, LDFLAGS was not renamed.

Using a well-known variable like LDFLAGS may result in accidental
override of the variable.

Kbuild generally uses KBUILD_ prefixed variables for the internally
appended options, so here is one more conversion to sanitize the
naming convention.

I did not touch Makefiles under tools/ since the tools build system
is a different world.

Signed-off-by: Masahiro Yamada 
Acked-by: Kirill A. Shutemov 
Reviewed-by: Palmer Dabbelt

mips: dts: mscc: enable spi and NOR flash support on ocelot PCB123

2018-07-31T17:34:34+00:00

Ocelot PCB123 has a SPI NOR connected on its SPI bus.

Signed-off-by: Alexandre Belloni 
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/20103/
Cc: Mark Brown 
Cc: James Hogan 
Cc: linux-spi@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Thomas Petazzoni 
Cc: Allan Nielsen

mips: dts: mscc: Add spi on Ocelot

2018-07-31T17:34:08+00:00

Add support for the SPI controller

Signed-off-by: Alexandre Belloni 
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/20101/
Cc: Mark Brown 
Cc: James Hogan 
Cc: linux-spi@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Thomas Petazzoni 
Cc: Allan Nielsen

MIPS: mscc: ocelot: add interrupt controller properties to GPIO controller

2018-07-30T17:34:28+00:00

The GPIO controller also serves as an interrupt controller for events
on the GPIO it handles.

An interrupt occurs whenever a GPIO line has changed.

Signed-off-by: Quentin Schulz 
Acked-by: Alexandre Belloni 
Reviewed-by: Linus Walleij 
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/20015/
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com

MIPS: ath79: Use the IRQ based GPIO key driver for the buttons

2018-07-28T02:29:53+00:00

Now that the GPIO driver support interrupts we don't need to poll the
buttons.

Signed-off-by: Alban Bedel 
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/15283/
Cc: linux-mips@linux-mips.org
Cc: Rob Herring 
Cc: Mark Rutland 
Cc: Ralf Baechle 
Cc: Antony Pavlov 
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

MIPS: ath79: Fix the USB PHY reset names

2018-07-26T18:21:28+00:00

The binding for the USB PHY went thru before the driver. However the
new version of the driver now use the PHY core support for reset, and
this expect the reset to be named "phy". So remove the "usb-" prefix
from the the reset names.

Signed-off-by: Alban Bedel 
Acked-by: Rob Herring 
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/15282/
Cc: linux-kernel@vger.kernel.org
Cc: Rob Herring 
Cc: Mark Rutland 
Cc: Ralf Baechle 
Cc: Antony Pavlov 
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org

MIPS: mscc: ocelot: add MIIM1 bus

2018-07-26T17:35:19+00:00

There is an additional MIIM (MDIO) bus in this SoC so let's declare it
in the dtsi.

This bus requires GPIO 14 and 15 pins that need to be muxed. There is no
support for internal PHY reset on this bus on the contrary of MIIM0 so
there is only one register address space and not two.

Signed-off-by: Quentin Schulz 
Acked-by: Alexandre Belloni 
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/20014/
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com

MIPS: mscc: ocelot: fix length of memory address space for MIIM

2018-07-26T17:34:58+00:00

The length of memory address space for MIIM0 is from 0x7107009c to
0x710700bf included which is 36 bytes long in decimal, or 0x24 bytes in
hexadecimal and not 0x36.

Fixes: 49b031690abe ("MIPS: mscc: Add switch to ocelot")

Signed-off-by: Quentin Schulz 
Acked-by: Alexandre Belloni 
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/20013/
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com

mips: mscc: build FIT image for Ocelot

2018-07-25T00:42:19+00:00

Ocelot now has a u-boot port, allow building FIT images instead of relying
on the legacy detection and builtin DTB.

Signed-off-by: Alexandre Belloni 
Reviewed-by: James Hogan 
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/19632/
Cc: Ralf Baechle 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org

MIPS: jz4780: DTS: Probe the spi-gpio driver from devicetree

2018-07-24T20:44:48+00:00

Make use of the spi-gpio driver to provide SPI support on the Ingenic
JZ4780 SoC using the pins that can be used with the SSI0 device as
GPIOs, until such time as we have support for the Ingenic SPI/SSI
controller.

[paul.burton@mips.com: Rewrite commit message.]

Signed-off-by: Mathieu Malaterre 
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/19489/
Cc: James Hogan 
Cc: Rob Herring 
Cc: Mark Rutland 
Cc: Ralf Baechle 
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org