linux.git/arch/mips/boot/dts, branch vsnprintf Linux kernel source tree MIPS: Loongson64: DTS: Really fix PCIe port nodes for ls7a 2024-11-23T10:53:21+00:00 Xi Ruoyao xry111@xry111.site 2024-11-23T03:57:37+00:00 4fbd66d8254cedfd1218393f39d83b6c07a01917 Fix the dtc warnings: arch/mips/boot/dts/loongson/ls7a-pch.dtsi:68.16-416.5: Warning (interrupt_provider): /bus@10000000/pci@1a000000: '#interrupt-cells' found, but node is not an interrupt provider arch/mips/boot/dts/loongson/ls7a-pch.dtsi:68.16-416.5: Warning (interrupt_provider): /bus@10000000/pci@1a000000: '#interrupt-cells' found, but node is not an interrupt provider arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dtb: Warning (interrupt_map): Failed prerequisite 'interrupt_provider' And a runtime warning introduced in commit 045b14ca5c36 ("of: WARN on deprecated #address-cells/#size-cells handling"): WARNING: CPU: 0 PID: 1 at drivers/of/base.c:106 of_bus_n_addr_cells+0x9c/0xe0 Missing '#address-cells' in /bus@10000000/pci@1a000000/pci_bridge@9,0 The fix is similar to commit d89a415ff8d5 ("MIPS: Loongson64: DTS: Fix PCIe port nodes for ls7a"), which has fixed the issue for ls2k (despite its subject mentions ls7a). Signed-off-by: Xi Ruoyao <xry111@xry111.site> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> 
Fix the dtc warnings:

    arch/mips/boot/dts/loongson/ls7a-pch.dtsi:68.16-416.5: Warning (interrupt_provider): /bus@10000000/pci@1a000000: '#interrupt-cells' found, but node is not an interrupt provider
    arch/mips/boot/dts/loongson/ls7a-pch.dtsi:68.16-416.5: Warning (interrupt_provider): /bus@10000000/pci@1a000000: '#interrupt-cells' found, but node is not an interrupt provider
    arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dtb: Warning (interrupt_map): Failed prerequisite 'interrupt_provider'

And a runtime warning introduced in commit 045b14ca5c36 ("of: WARN on
deprecated #address-cells/#size-cells handling"):

    WARNING: CPU: 0 PID: 1 at drivers/of/base.c:106 of_bus_n_addr_cells+0x9c/0xe0
    Missing '#address-cells' in /bus@10000000/pci@1a000000/pci_bridge@9,0

The fix is similar to commit d89a415ff8d5 ("MIPS: Loongson64: DTS: Fix PCIe
port nodes for ls7a"), which has fixed the issue for ls2k (despite its
subject mentions ls7a).

Signed-off-by: Xi Ruoyao <xry111@xry111.site>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
mips: dts: realtek: Add SPI NAND controller 2024-11-20T22:45:45+00:00 Chris Packham chris.packham@alliedtelesis.co.nz 2024-10-15T22:54:33+00:00 5a38a5d40f2fa01591ab961ff37385a74b1ec7e1 Add the SPI-NAND controller on the RTL9300 family of devices. This supports serial/dual/quad data width and DMA for read/program operations. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> 
Add the SPI-NAND controller on the RTL9300 family of devices. This
supports serial/dual/quad data width and DMA for read/program
operations.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
MIPS: mobileye: eyeq6h: add OLB nodes OLB and remove fixed clocks 2024-11-15T08:35:39+00:00 Théo Lebrun theo.lebrun@bootlin.com 2024-11-06T16:04:01+00:00 1be858f7fafe73afba1e2af9fc6dfce04f411354 Change the declaration of clocks: remove all fixed clocks and declare system-controllers (OLB) as clock providers. Remove eyeq6h-fixed-clocks.dtsi and move the crystal clock to the main eyeq6h.dtsi file. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> 
Change the declaration of clocks: remove all fixed clocks and declare
system-controllers (OLB) as clock providers.

Remove eyeq6h-fixed-clocks.dtsi and move the crystal clock to the main
eyeq6h.dtsi file.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
MIPS: mobileye: eyeq5: use OLB as provider for fixed factor clocks 2024-11-15T08:35:20+00:00 Théo Lebrun theo.lebrun@bootlin.com 2024-11-06T16:04:00+00:00 d3c3c283afbe17a656d546c6881b8e01071b906c Change the structure of the clock tree: rather than individual devicetree nodes registering each fixed factor clock derived from OLB PLLs, have the OLB node provide the necessary clocks. Remove eyeq5-clocks.dtsi and move the three remaining "fixed-clock"s to the main eyeq5.dtsi file. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> 
Change the structure of the clock tree: rather than individual
devicetree nodes registering each fixed factor clock derived from OLB
PLLs, have the OLB node provide the necessary clocks.

Remove eyeq5-clocks.dtsi and move the three remaining "fixed-clock"s to
the main eyeq5.dtsi file.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
mips: dts: realtek: Add I2C controllers 2024-11-12T14:51:21+00:00 Chris Packham chris.packham@alliedtelesis.co.nz 2024-11-06T00:18:34+00:00 56131e6d1fcce8e7359a2445711cc1a4ddb8325c Add the I2C controllers that are part of the RTL9300 SoC. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> 
Add the I2C controllers that are part of the RTL9300 SoC.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
mips: dts: realtek: Add syscon-reboot node 2024-11-12T14:51:09+00:00 Chris Packham chris.packham@alliedtelesis.co.nz 2024-11-06T00:18:33+00:00 5ec37be43fe73c21b4b52c4d7f9c400221bdbacf The board level reset on systems using the RTL9302 can be driven via the switch. Use a syscon-reboot node to represent this. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> 
The board level reset on systems using the RTL9302 can be driven via the
switch. Use a syscon-reboot node to represent this.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
MIPS: mobileye: eyeq6h-epm6: Use eyeq6h in the board device tree 2024-10-30T22:45:59+00:00 Gregory CLEMENT gregory.clement@bootlin.com 2024-10-08T09:18:47+00:00 1aa6755387880dcdd2de2069f4fc6c21de8e5291 There is currently no eyeq6 compatible string defined in the binding documentation. Only eyeq6h version is defined, so let's use it. Note that there are actually no codes relying on eyeq6h; the purpose of this patch is mainly to be coherent with the documentation. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> 
There is currently no eyeq6 compatible string defined in the binding
documentation. Only eyeq6h version is defined, so let's use it.

Note that there are actually no codes relying on eyeq6h; the purpose
of this patch is mainly to be coherent with the documentation.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
mips: bmips: bcm6358/6368: define required brcm,bmips-cbr-reg 2024-10-30T22:45:53+00:00 Christian Marangi ansuelsmth@gmail.com 2024-10-01T15:23:59+00:00 7c43938f6581d08bb7a79286b996a32c0945bc49 For the bcm6358/6368 SoC the brcm,bmips-cbr-reg due to bootloader misconfiguration or HW bug from running the system from TP1. A workaround is now present to handle broken system that suffer from this bug hence add the now required property. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202409251520.pE12GzHd-lkp@intel.com/ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> 
For the bcm6358/6368 SoC the brcm,bmips-cbr-reg due to bootloader
misconfiguration or HW bug from running the system from TP1.

A workaround is now present to handle broken system that suffer from
this bug hence add the now required property.

Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202409251520.pE12GzHd-lkp@intel.com/
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
mips: dts: realtek: Add RTL9302C board 2024-07-12T11:12:16+00:00 Chris Packham chris.packham@alliedtelesis.co.nz 2024-07-10T04:35:24+00:00 74beefb5935a67f9fa60f8103e3f69d42d6a08d7 Add support for the RTL9302 SoC and the RTL9302C_2xRTL8224_2XGE reference board. The RTL930x family of SoCs are Realtek switches with an embedded MIPS core (800MHz 34Kc). Most of the peripherals are similar to the RTL838x SoC and can make use of many existing drivers. Add in full DSA switch support is still a work in progress. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> 
Add support for the RTL9302 SoC and the RTL9302C_2xRTL8224_2XGE
reference board.

The RTL930x family of SoCs are Realtek switches with an embedded MIPS
core (800MHz 34Kc). Most of the peripherals are similar to the RTL838x
SoC and can make use of many existing drivers.

Add in full DSA switch support is still a work in progress.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
mips: dts: realtek: add device_type property to cpu node 2024-07-12T11:11:26+00:00 Chris Packham chris.packham@alliedtelesis.co.nz 2024-07-10T04:35:16+00:00 75eb0cbe6e2220feffc7c6219b7dc80c56068bb9 Add device_type = "cpu" to the cpu node for the rtl838x SoC. This resolves the following dtbs_check complaint: cpus: cpu@0: 'cache-level' is a required property Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Marek Behún <kabel@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> 
Add device_type = "cpu" to the cpu node for the rtl838x SoC. This
resolves the following dtbs_check complaint:

 cpus: cpu@0: 'cache-level' is a required property

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>