Add new fpga families where Microblaze can run on.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add missing release version code for v9.6 and v10.0.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add missing release version code for v9.4 and v9.5.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add missing target architectures - virtex7, ultrascale virtex
and ultrascale kintex.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

PVR version code was missing in the cpu_ver_lookup table for the following
versions: 8.50.b 8.50.c 9.2 9.3

This caused /proc/cpuinfo to display "CPU-Ver: Unknown" for these versions.

This was detected and the patch tested with MicroBlaze version 8.50.c.
The other codes were taken from the Xilinx MicroBlaze Processor Reference
Guides UG081 (v14.7) and UG984 (v2014.1).

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add PVR value for MB 8.50.a.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add support for CCF for Microblaze.

Old binding:
system_timer: system-timer@41c00000 {
	clock-frequency = <75000000>;
	...
}

New binding:
system_timer: system-timer@41c00000 {
	clocks = <&clk_bus>;
	...
}

Both should be supported for a while

Microblaze clock binding:
clocks {
	#address-cells = <1>;
	#size-cells = <0>;
	clk_bus: bus {
		#clock-cells = <0>;
		clock-frequency = <75000000>;
		clock-output-names = "bus";
		compatible = "fixed-clock";
		reg = <1>;
	} ;
	clk_cpu: cpu {
		#clock-cells = <0>;
		clock-frequency = <75000000>;
		clock-output-names = "cpu";
		compatible = "fixed-clock";
		reg = <0>;
	} ;
} ;

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Extend PVR reg decoding.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Update PVR values based on reference manual.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Fix coding style issues reported by checkpatch.pl.

Signed-off-by: Michal Simek <monstr@monstr.eu>