linux.git/arch/microblaze/kernel/cpu/cache.c, branch v2.6.37

microblaze: Remove compilation warnings in cache macro

2010-05-13T08:55:47+00:00

CC      arch/microblaze/kernel/cpu/cache.o
arch/microblaze/kernel/cpu/cache.c: In function '__invalidate_dcache_range_wb':
arch/microblaze/kernel/cpu/cache.c:398: warning: ISO C90 forbids mixed declarations and code
arch/microblaze/kernel/cpu/cache.c: In function '__flush_dcache_range_wb':
arch/microblaze/kernel/cpu/cache.c:509: warning: ISO C90 forbids mixed declara

Signed-off-by: Michal Simek

microblaze: Optimize CACHE_LOOP_LIMITS and CACHE_RANGE_LOOP macros

2010-05-06T09:22:00+00:00

1. Remove CACHE_ALL_LOOP2 macro because it is identical to CACHE_ALL_LOOP
2. Change BUG_ON to WARN_ON
3. Remove end aligned from CACHE_LOOP_LIMITS.
C implementation do not need aligned end address and ASM code do aligned
in their macros
4. ASM optimized  CACHE_RANGE_LOOP_1/2 macros needs to get aligned end address.
Because end address is compound from start + size, end address is the first address
which is exclude.

Here is the corresponding code which describe it.
+       int align = ~(line_length - 1);
+       end = ((end & align) == end) ? end - line_length : end & align;

a) end is aligned:
it is necessary to subtruct line length because we don't want to work with
next cacheline
b) end address is not aligned:
Just align it to be ready for ASM code.

Signed-off-by: Michal Simek

microblaze: Fix typo fault in cache code

2010-05-06T09:21:59+00:00

Copy & paste error.

Signed-off-by: Michal Simek

microblaze: Add define for ASM_LOOP

2010-03-11T13:12:50+00:00

It is default option but both options must be measured.

Signed-off-by: Michal Simek

microblaze: remove trailing space in messages

2010-03-11T13:09:29+00:00

Signed-off-by: Frans Pop 
Cc: microblaze-uclinux@itee.uq.edu.au
Cc: Michal Simek 
Signed-off-by: Michal Simek

microblaze: Move cache function to cache.c

2010-03-11T13:07:57+00:00

It is better to have init cache handling on one place.

Signed-off-by: Michal Simek

microblaze: Fix cache loop function for cache range

2010-02-24T12:18:29+00:00

I create wrong asm code but none test shows that this part of code is wrong.
I am not convinces that were good idea to create asm optimized macros
for caches. The reason is that there is not optimization with previous code
that's why make sense to add old code and do some benchmarking which
functions are faster.

Signed-off-by: Michal Simek

microblaze: Support for WB cache

2009-12-14T07:45:10+00:00

Microblaze version 7.20.d is the first MB version which can be run
on MMU linux. Please do not used previous version because they contain
HW bug.
Based on WB support was necessary to redesign whole cache design.
Microblaze versions from 7.20.a don't need to disable IRQ and cache
before working with them that's why there are special structures for it.

Signed-off-by: Michal Simek

microblaze: Fix cache_line_lenght

2009-12-14T07:44:57+00:00

We used cache_line as cache_line_lenght. For this reason
we did cache flushing 4 times longer than was necessary.

Signed-off-by: Michal Simek

microblaze: Do not check use_dcache

2009-04-23T14:27:31+00:00

It is not necessary to check cpuinfo.use_dcache because
this checking is done in function which call that functions

Signed-off-by: Michal Simek