linux.git/arch/arm, branch v2.6.15

[ARM] 3210/1: add missing memory barrier helper for NPTL support

2005-12-19T22:20:51+00:00

Patch from Nicolas Pitre

Strictly speaking, the NPTL kernel helpers are required for pre ARMv6
only.  They are available on ARMv6+ as well for obvious compatibility
reasons.  However there are cases where extra memory barriers are needed
when using an SMP ARMv6 machine but not on pre-ARMv6.

This patch adds a memory barrier kernel helper that glibc can use as
needed for pre-ARMv6 binaries to be forward compatible with an SMP
kernel on ARMv6, as well as the necessary dmb instructions to the
cmpxchg helper.

Signed-off-by: Nicolas Pitre 
Acked-by: Daniel Jacobowitz 
Signed-off-by: Russell King

[ARM] Fix sys_sendto and sys_recvfrom 6-arg syscalls

2005-12-17T15:25:42+00:00

Rather than providing more wrappers for 6-arg syscalls, arrange for
them to be supported as standard.  This just means that we always
store the 6th argument on the stack, rather than in the wrappers.

This means we eliminate the wrappers for:
* sys_futex
* sys_arm_fadvise64_64
* sys_mbind
* sys_ipc

Signed-off-by: Russell King

[ARM] 3205/1: Handle new EABI relocations when loading kernel modules.

2005-12-14T22:04:22+00:00

Patch from Daniel Jacobowitz

Handle new EABI relocations when loading kernel modules.  This is
necessary for CONFIG_AEABI kernels, and also for some broken
(since fixed) old ABI toolchains.

Signed-off-by: Daniel Jacobowitz 
Signed-off-by: Russell King

[ARM] 3201/1: PXA27x: Prevent hangup during resume due to inadvertedly enabling MBREQ (replaces: 3198/1)

2005-12-12T16:44:05+00:00

Patch from Lothar Wassmann

The patch makes sure, that the ouptut functions of pins are restored
before restoring the Alternat Function settings, preventing pins from
being intermediately configured for undefined or unwanted alternate
functions.

Here is the original comment:
I've got a PXA270 system that uses GPIO80 as nCS4. This system did
hang on resume. Digging into the problem I found that the processor
stalled immediately when restoring the GAFR2_U register which restored
the alternate function for GPIO80. Since the GPDR registers were
restored after the GAFR registers, the offending GPIO was configured
as input at this point.
Thus the alternate function that was in effect after restoring the
GAFR was in fact the input function "MBREQ" instead of the output
function "nCS4". The "PXA27x Processor Family Developer's Manual"
(Footnote in Table 6-1 on page 6-3) states that:
"The MBREQ alternate function must not be enabled until the PSSR[RDH]
bit field is cleared. For more details, see Table 3-15, "PSSR Bit
Definitions" on page 3-71."

There is another note in the Developer's Manual (chapter 24.4.2
"GPIO operation as Alternate Function" on page 24-4)
stating that:
"Configuring a GPIO for an alternate function that is not defined for
it causes unpredictable results."

Since some GPIOs have no input function defined, and to prevent
inadvertedly programming the MBREQ function on some pin, the GAFR
registers should be restored after the GPDR registers have been
restored.

Additional provisions have to be made when the MBREQ function is
actually required. The corresponding GAFR bits should not be restored
with the regular GAFR restore, but must be set only after the PSSR
bits have been cleared.

Signed-off-by: Lothar Wassmann 
Signed-off-by: Russell King

[ARM] 3200/1: Singlestep over ARM BX and BLX instructions using ptrace fix

2005-12-10T11:59:15+00:00

Patch from Nikola Valerjev

Single stepping an application using ptrace() fails over ARM instructions BX and BLX.

Steps to reproduce:

Compile and link the following files

main.c
-----
void foo();
int main() {
    foo();
    return 0;
}

foo.s
-----
	.text
	.globl foo
foo:
	BX LR

Using ptrace() functionality, run to main(), and start singlestepping.
Singlestep over \"BX LR\" instruction won\'t transfer the control back
to main, but run the code to completion.

This problems seems to be in the function get_branch_address() in
arch/arm/kernel/ptrace.c. The function doesn\'t seem to recognize BX
and BLX instructions as branches. BX and BLX instructions can be used
to convert from ARM to Thumb mode if the target address has the low
bit set. However, they are also perfectly legal in the ARM only mode.
Although other things in the kernel seem to indicate that only ARM
mode is accepted (and not Thumb), many compilers will generate BX
and BLX instructions even when generating ARM only code.

Signed-off-by: Nikola Valerjev 
Signed-off-by: Russell King

[ARM] 3188/1: Add missing i2c dependency for Akita

2005-12-01T15:52:47+00:00

Patch from Richard Purdie

Akita requires inbuilt kernel i2c support for its GPIOs. Add this
requirement to Kconfig and update the defconfig to match.

Signed-off-by: Richard Purdie 
Signed-off-by: Russell King

[ARM] Fix IXDP425 setup bug

2005-12-01T15:50:35+00:00

There is a typo in the ARM IXDP425 setup definition that mistakenly tries
to use UART1's IRQ for UART2's traffic.

Signed-off-by: Andrew Morton 
Signed-off-by: Russell King

[ARM SMP] Disable lazy flush_dcache_page for SMP

2005-11-30T16:02:54+00:00

Lazy flush_dcache_page() causes userspace instability on SMP
platforms, so disable it for now.

Signed-off-by: Russell King

[ARM] 3180/1: Update Zaurus defconfigs

2005-11-28T18:08:45+00:00

Patch from Richard Purdie

This updates the Zaurus defconfigs. Poodle gets merged into
corgi_defconfig and support for tosa and akita is enabled.

Signed-off-by: Richard Purdie 
Signed-off-by: Russell King

[ARM] 3179/1: Update/correct Zaurus Kconfig entries

2005-11-28T18:08:44+00:00

Patch from Richard Purdie

Add iWMMX Extentions for the pxa27x based Zaurus models and
fix a couple of minor mistakes in the PXA Kconfig file.

Signed-off-by: Richard Purdie 
Signed-off-by: Russell King