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<title>linux.git/arch/arm64/include/asm/assembler.h, branch v3.14</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>arm64: asm: add CPU_LE &amp; CPU_BE assembler helpers</title>
<updated>2013-10-25T14:59:38+00:00</updated>
<author>
<name>Matthew Leach</name>
<email>matthew.leach@arm.com</email>
</author>
<published>2013-10-11T13:52:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=e68bedaa03c950ae8045e7899e7a6b2a97d1bf41'/>
<id>e68bedaa03c950ae8045e7899e7a6b2a97d1bf41</id>
<content type='text'>
Add CPU_LE and CPU_BE to select assembler code in little and big
endian configurations respectively.

Signed-off-by: Matthew Leach &lt;matthew.leach@arm.com&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
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<pre>
Add CPU_LE and CPU_BE to select assembler code in little and big
endian configurations respectively.

Signed-off-by: Matthew Leach &lt;matthew.leach@arm.com&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>arm64: compat: correct register concatenation for syscall wrappers</title>
<updated>2013-10-25T14:59:36+00:00</updated>
<author>
<name>Matthew Leach</name>
<email>matthew.leach@arm.com</email>
</author>
<published>2013-10-11T13:52:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=55b89540b0d8d031f90e3d711ec0df3f797ecc61'/>
<id>55b89540b0d8d031f90e3d711ec0df3f797ecc61</id>
<content type='text'>
The arm64 port contains wrappers for arm32 syscalls that pass 64-bit
values. These wrappers concatenate the two registers to hold a 64-bit
value in a single X register. On BE, however, the lower and higher
words are swapped.

Create a new assembler macro, regs_to_64, that when on BE systems
swaps the registers in the orr instruction.

Acked-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Matthew Leach &lt;matthew.leach@arm.com&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
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<pre>
The arm64 port contains wrappers for arm32 syscalls that pass 64-bit
values. These wrappers concatenate the two registers to hold a 64-bit
value in a single X register. On BE, however, the lower and higher
words are swapped.

Create a new assembler macro, regs_to_64, that when on BE systems
swaps the registers in the orr instruction.

Acked-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Matthew Leach &lt;matthew.leach@arm.com&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>arm64: debug: fix mdscr.ss check when enabling debug exceptions</title>
<updated>2013-05-17T17:24:19+00:00</updated>
<author>
<name>Will Deacon</name>
<email>will.deacon@arm.com</email>
</author>
<published>2013-05-17T16:41:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=3126976be64bfb4c87297cb022ca815212079aec'/>
<id>3126976be64bfb4c87297cb022ca815212079aec</id>
<content type='text'>
When we take an exception at EL1, we only want to enable debug
exceptions if we're not currently stepping, otherwise we can easily get
stuck in a loop stepping into interrupt handlers.

Unfortunately, the current code tests the wrong bit in the mdscr, so fix
that.

Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</content>
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<pre>
When we take an exception at EL1, we only want to enable debug
exceptions if we're not currently stepping, otherwise we can easily get
stuck in a loop stepping into interrupt handlers.

Unfortunately, the current code tests the wrong bit in the mdscr, so fix
that.

Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>arm64: move vector entry macro to assembler.h</title>
<updated>2012-12-05T11:26:47+00:00</updated>
<author>
<name>Marc Zyngier</name>
<email>marc.zyngier@arm.com</email>
</author>
<published>2012-10-19T16:37:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=dc637f1fdaa6f335271a0341fef3914b80ab929c'/>
<id>dc637f1fdaa6f335271a0341fef3914b80ab929c</id>
<content type='text'>
This macro is also useful to other bits defining vectors (hypervisor
stub, KVM...).

Move it to a common location.

Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</content>
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<pre>
This macro is also useful to other bits defining vectors (hypervisor
stub, KVM...).

Move it to a common location.

Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: Assembly macros and definitions</title>
<updated>2012-09-17T09:24:44+00:00</updated>
<author>
<name>Catalin Marinas</name>
<email>catalin.marinas@arm.com</email>
</author>
<published>2012-03-05T11:49:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=0be7320a635c2e434e8b67e0e9474a85ceb421c4'/>
<id>0be7320a635c2e434e8b67e0e9474a85ceb421c4</id>
<content type='text'>
This patch introduces several assembly macros and definitions used in
the .S files across arch/arm64/ like IRQ disabling/enabling, together
with asm-offsets.c.

Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Acked-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Acked-by: Olof Johansson &lt;olof@lixom.net&gt;
Acked-by: Santosh Shilimkar &lt;santosh.shilimkar@ti.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch introduces several assembly macros and definitions used in
the .S files across arch/arm64/ like IRQ disabling/enabling, together
with asm-offsets.c.

Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Acked-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Acked-by: Olof Johansson &lt;olof@lixom.net&gt;
Acked-by: Santosh Shilimkar &lt;santosh.shilimkar@ti.com&gt;
</pre>
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</content>
</entry>
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