<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/arch/arm64/boot/dts/microchip, branch master</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>arm64: dts: microchip: add EV23X71A board</title>
<updated>2026-03-20T08:56:22+00:00</updated>
<author>
<name>Robert Marko</name>
<email>robert.marko@sartura.hr</email>
</author>
<published>2026-03-02T11:20:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=711cca0f1cfef57018654b969da4041c2bab68d3'/>
<id>711cca0f1cfef57018654b969da4041c2bab68d3</id>
<content type='text'>
Microchip EV23X71A is an LAN9696 based evaluation board.

Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
Reviewed-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
Acked-by: Daniel Machon &lt;daniel.machon@microchip.com&gt;
Tested-by: Daniel Machon &lt;daniel.machon@microchip.com&gt;
Link: https://lore.kernel.org/r/20260302112153.464422-7-robert.marko@sartura.hr
Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Microchip EV23X71A is an LAN9696 based evaluation board.

Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
Reviewed-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
Acked-by: Daniel Machon &lt;daniel.machon@microchip.com&gt;
Tested-by: Daniel Machon &lt;daniel.machon@microchip.com&gt;
Link: https://lore.kernel.org/r/20260302112153.464422-7-robert.marko@sartura.hr
Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: dts: microchip: add LAN969x support</title>
<updated>2026-03-20T08:56:20+00:00</updated>
<author>
<name>Robert Marko</name>
<email>robert.marko@sartura.hr</email>
</author>
<published>2026-03-02T11:20:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=1effec9834710ec417861634c32208edcd2fcb2a'/>
<id>1effec9834710ec417861634c32208edcd2fcb2a</id>
<content type='text'>
Add support for Microchip LAN969x switch SoC series by adding the SoC DTSI.

Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
Reviewed-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
Acked-by: Daniel Machon &lt;daniel.machon@microchip.com&gt;
Link: https://lore.kernel.org/r/20260302112153.464422-5-robert.marko@sartura.hr
Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for Microchip LAN969x switch SoC series by adding the SoC DTSI.

Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
Reviewed-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
Acked-by: Daniel Machon &lt;daniel.machon@microchip.com&gt;
Link: https://lore.kernel.org/r/20260302112153.464422-5-robert.marko@sartura.hr
Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: dts: microchip: add LAN969x clock header file</title>
<updated>2026-03-20T08:56:19+00:00</updated>
<author>
<name>Robert Marko</name>
<email>robert.marko@sartura.hr</email>
</author>
<published>2026-03-02T11:20:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=229eeb0ad913c1bb2dd6027e5983d1e4c409abd0'/>
<id>229eeb0ad913c1bb2dd6027e5983d1e4c409abd0</id>
<content type='text'>
LAN969x uses hardware clock indexes, so document theses in a header to make
them humanly readable.

Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
Reviewed-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
Link: https://lore.kernel.org/r/20260302112153.464422-4-robert.marko@sartura.hr
Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
LAN969x uses hardware clock indexes, so document theses in a header to make
them humanly readable.

Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
Reviewed-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
Link: https://lore.kernel.org/r/20260302112153.464422-4-robert.marko@sartura.hr
Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: dts: microchip: sparx5: Fix CPU node "enable-method" property dependencies</title>
<updated>2025-04-07T15:02:43+00:00</updated>
<author>
<name>Rob Herring (Arm)</name>
<email>robh@kernel.org</email>
</author>
<published>2025-04-04T02:59:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=ec32344d2a3b841d096c12cffe8e620ad117a6a0'/>
<id>ec32344d2a3b841d096c12cffe8e620ad117a6a0</id>
<content type='text'>
The "spin-table" enable-method requires "cpu-release-addr" property,
so add a dummy entry. It is assumed the bootloader will fill in the
correct values.

Signed-off-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Reviewed-by: Daniel Machon &lt;daniel.machon@microchip.com&gt;
Tested-by: Daniel Machon &lt;daniel.machon@microchip.com&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The "spin-table" enable-method requires "cpu-release-addr" property,
so add a dummy entry. It is assumed the bootloader will fill in the
correct values.

Signed-off-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Reviewed-by: Daniel Machon &lt;daniel.machon@microchip.com&gt;
Tested-by: Daniel Machon &lt;daniel.machon@microchip.com&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: dts: microchip: sparx5_pcb135: move non-MMIO nodes out of axi</title>
<updated>2024-06-04T17:53:22+00:00</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzysztof.kozlowski@linaro.org</email>
</author>
<published>2024-06-04T11:49:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=3a94fa4cb86e96103657ba3550ee68b424269613'/>
<id>3a94fa4cb86e96103657ba3550ee68b424269613</id>
<content type='text'>
simple-bus nodes, so the "axi" node, should not have non-MMIO children
as pointed out by simple-bus schema dtbs_check:

  sparx5_pcb135_emmc.dtb: axi@600000000: sfp-eth60: {'compatible': ... should not be valid under {'type': 'object'}
    from schema $id: http://devicetree.org/schemas/simple-bus.yaml#

Reported-by: Rob Herring &lt;robh@kernel.org&gt;
Closes: https://lore.kernel.org/all/CAL_Jsq+PtL3HTKkA_gwTjb_i1mFZ+wW+qwin34HMYmwW7oNDFw@mail.gmail.com/
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
simple-bus nodes, so the "axi" node, should not have non-MMIO children
as pointed out by simple-bus schema dtbs_check:

  sparx5_pcb135_emmc.dtb: axi@600000000: sfp-eth60: {'compatible': ... should not be valid under {'type': 'object'}
    from schema $id: http://devicetree.org/schemas/simple-bus.yaml#

Reported-by: Rob Herring &lt;robh@kernel.org&gt;
Closes: https://lore.kernel.org/all/CAL_Jsq+PtL3HTKkA_gwTjb_i1mFZ+wW+qwin34HMYmwW7oNDFw@mail.gmail.com/
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: dts: microchip: sparx5_pcb134: move non-MMIO nodes out of axi</title>
<updated>2024-06-04T17:53:22+00:00</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzysztof.kozlowski@linaro.org</email>
</author>
<published>2024-06-04T11:49:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=fe7c551ea03e0df729966e33c58f9955f7408208'/>
<id>fe7c551ea03e0df729966e33c58f9955f7408208</id>
<content type='text'>
simple-bus nodes, so the "axi" node, should not have non-MMIO children
as pointed out by simple-bus schema dtbs_check:

  sparx5_pcb134.dtb: axi@600000000: i2c-mux-0: {'compatible': ... should not be valid under {'type': 'object'}
    from schema $id: http://devicetree.org/schemas/simple-bus.yaml#

Reported-by: Rob Herring &lt;robh@kernel.org&gt;
Closes: https://lore.kernel.org/all/CAL_Jsq+PtL3HTKkA_gwTjb_i1mFZ+wW+qwin34HMYmwW7oNDFw@mail.gmail.com/
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
simple-bus nodes, so the "axi" node, should not have non-MMIO children
as pointed out by simple-bus schema dtbs_check:

  sparx5_pcb134.dtb: axi@600000000: i2c-mux-0: {'compatible': ... should not be valid under {'type': 'object'}
    from schema $id: http://devicetree.org/schemas/simple-bus.yaml#

Reported-by: Rob Herring &lt;robh@kernel.org&gt;
Closes: https://lore.kernel.org/all/CAL_Jsq+PtL3HTKkA_gwTjb_i1mFZ+wW+qwin34HMYmwW7oNDFw@mail.gmail.com/
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: dts: microchip: sparx5_pcb135: drop duplicated NOR flash</title>
<updated>2024-04-08T15:56:30+00:00</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzk@kernel.org</email>
</author>
<published>2024-04-05T19:04:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=6c7c4b91aa43543c9f967120a6eabd451a0927d4'/>
<id>6c7c4b91aa43543c9f967120a6eabd451a0927d4</id>
<content type='text'>
Since beginning the DTS extended the SPI0 in two places adding two SPI
muxes, each with same SPI NOR flash.  Both used exactly the same
chip-selects, so this was clearly buggy code.  Then in commit
d0f482bb06f9 ("arm64: dts: sparx5: Add the Sparx5 switch node") one SPI
mux was removed, while keeping the SPI NOR flash node.

This still leaves duplicated SPI nodes under same chip select 0,
reported by dtc W=1 warnings:

  sparx5_pcb135_board.dtsi:92.10-96.4: Warning (unique_unit_address_if_enabled): /axi@600000000/spi@600104000/flash@0: duplicate unit-address (also used in node /axi@600000000/spi@600104000/spi@0)

Steen Hegelund confirmed that in fact there is a SPI mux, thus remove
the duplicated node without the mux.

Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
Tested-by: Steen Hegelund &lt;Steen.Hegelund@microchip.com&gt;
Reviewed-by: Steen Hegelund &lt;Steen.Hegelund@microchip.com&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Since beginning the DTS extended the SPI0 in two places adding two SPI
muxes, each with same SPI NOR flash.  Both used exactly the same
chip-selects, so this was clearly buggy code.  Then in commit
d0f482bb06f9 ("arm64: dts: sparx5: Add the Sparx5 switch node") one SPI
mux was removed, while keeping the SPI NOR flash node.

This still leaves duplicated SPI nodes under same chip select 0,
reported by dtc W=1 warnings:

  sparx5_pcb135_board.dtsi:92.10-96.4: Warning (unique_unit_address_if_enabled): /axi@600000000/spi@600104000/flash@0: duplicate unit-address (also used in node /axi@600000000/spi@600104000/spi@0)

Steen Hegelund confirmed that in fact there is a SPI mux, thus remove
the duplicated node without the mux.

Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
Tested-by: Steen Hegelund &lt;Steen.Hegelund@microchip.com&gt;
Reviewed-by: Steen Hegelund &lt;Steen.Hegelund@microchip.com&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: dts: microchip: sparx5_pcb134: drop duplicated NOR flash</title>
<updated>2024-04-08T15:56:14+00:00</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzk@kernel.org</email>
</author>
<published>2024-04-05T19:04:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=f1595d501ea49ea49ff0e4a6beec4929c1618cb3'/>
<id>f1595d501ea49ea49ff0e4a6beec4929c1618cb3</id>
<content type='text'>
Since beginning the DTS extended the SPI0 in two places adding two SPI
muxes, each with same SPI NOR flash.  Both used exactly the same
chip-selects, so this was clearly buggy code.  Then in commit
d0f482bb06f9 ("arm64: dts: sparx5: Add the Sparx5 switch node") one SPI
mux was removed, while keeping the SPI NOR flash node.

This still leaves duplicated SPI nodes under same chip select 0,
reported by dtc W=1 warnings:

  sparx5_pcb134_board.dtsi:277.10-281.4: Warning (unique_unit_address_if_enabled): /axi@600000000/spi@600104000/flash@0: duplicate unit-address (also used in node /axi@600000000/spi@600104000/spi@0)

Steen Hegelund confirmed that in fact there is a SPI mux, thus remove
the duplicated node without the mux.

Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
Tested-by: Steen Hegelund &lt;Steen.Hegelund@microchip.com&gt;
Reviewed-by: Steen Hegelund &lt;Steen.Hegelund@microchip.com&gt;
Reviewed-by: Steen Hegelund &lt;Steen.Hegelund@microchip.com&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Since beginning the DTS extended the SPI0 in two places adding two SPI
muxes, each with same SPI NOR flash.  Both used exactly the same
chip-selects, so this was clearly buggy code.  Then in commit
d0f482bb06f9 ("arm64: dts: sparx5: Add the Sparx5 switch node") one SPI
mux was removed, while keeping the SPI NOR flash node.

This still leaves duplicated SPI nodes under same chip select 0,
reported by dtc W=1 warnings:

  sparx5_pcb134_board.dtsi:277.10-281.4: Warning (unique_unit_address_if_enabled): /axi@600000000/spi@600104000/flash@0: duplicate unit-address (also used in node /axi@600000000/spi@600104000/spi@0)

Steen Hegelund confirmed that in fact there is a SPI mux, thus remove
the duplicated node without the mux.

Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
Tested-by: Steen Hegelund &lt;Steen.Hegelund@microchip.com&gt;
Reviewed-by: Steen Hegelund &lt;Steen.Hegelund@microchip.com&gt;
Reviewed-by: Steen Hegelund &lt;Steen.Hegelund@microchip.com&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: dts: microchip: sparx5_pcb135: drop LED unit addresses</title>
<updated>2024-04-08T15:56:09+00:00</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzk@kernel.org</email>
</author>
<published>2024-04-05T19:04:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=5945df4de0e2117edccc65ebbfd6d21f01967cd5'/>
<id>5945df4de0e2117edccc65ebbfd6d21f01967cd5</id>
<content type='text'>
GPIO leds should not have unit addresses (no "reg" property), as
reported by dtc W=1 warnings:

  sparx5_pcb135_board.dtsi:18.9-22.5: Warning (unit_address_vs_reg): /leds/led@0: node has a unit name, but no reg or ranges property

Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
Reviewed-by: Steen Hegelund &lt;Steen.Hegelund@microchip.com&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
GPIO leds should not have unit addresses (no "reg" property), as
reported by dtc W=1 warnings:

  sparx5_pcb135_board.dtsi:18.9-22.5: Warning (unit_address_vs_reg): /leds/led@0: node has a unit name, but no reg or ranges property

Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
Reviewed-by: Steen Hegelund &lt;Steen.Hegelund@microchip.com&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: dts: microchip: sparx5_pcb134: drop LED unit addresses</title>
<updated>2024-04-08T15:56:05+00:00</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzk@kernel.org</email>
</author>
<published>2024-04-05T19:04:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=55fb5a97ebe0ab763dc0526ac7ff626815a241a3'/>
<id>55fb5a97ebe0ab763dc0526ac7ff626815a241a3</id>
<content type='text'>
GPIO leds should not have unit addresses (no "reg" property), as
reported by dtc W=1 warnings:

  sparx5_pcb134_board.dtsi:18.9-21.5: Warning (unit_address_vs_reg): /leds/led@0: node has a unit name, but no reg or ranges property

Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
Reviewed-by: Steen Hegelund &lt;Steen.Hegelund@microchip.com&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
GPIO leds should not have unit addresses (no "reg" property), as
reported by dtc W=1 warnings:

  sparx5_pcb134_board.dtsi:18.9-21.5: Warning (unit_address_vs_reg): /leds/led@0: node has a unit name, but no reg or ranges property

Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
Reviewed-by: Steen Hegelund &lt;Steen.Hegelund@microchip.com&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
