<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/arch/arm64/boot/dts/broadcom, branch master</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>arm64: dts: broadcom: bcm2712: Move non simple-bus nodes to root level</title>
<updated>2026-03-20T17:17:30+00:00</updated>
<author>
<name>Rob Herring (Arm)</name>
<email>robh@kernel.org</email>
</author>
<published>2026-03-20T15:48:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=0acb1de2b4df426a62dba33bcd80f3939636f97b'/>
<id>0acb1de2b4df426a62dba33bcd80f3939636f97b</id>
<content type='text'>
The 'gpu' and 'firmware' nodes are not MMIO devices, so they should not
be under a 'simple-bus', but at the root level.

Signed-off-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/20260320154809.1246064-2-robh@kernel.org
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The 'gpu' and 'firmware' nodes are not MMIO devices, so they should not
be under a 'simple-bus', but at the root level.

Signed-off-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/20260320154809.1246064-2-robh@kernel.org
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: dts: broadcom: bcm2712-d-rpi-5-b: update uart10 interrupt</title>
<updated>2026-03-16T20:56:26+00:00</updated>
<author>
<name>Gregor Herburger</name>
<email>gregor.herburger@linutronix.de</email>
</author>
<published>2026-02-26T08:55:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=18d4a06e10051681de074a9250e54afc1f3ee312'/>
<id>18d4a06e10051681de074a9250e54afc1f3ee312</id>
<content type='text'>
On the -d revision of bcm2712 the uart interrupt is on 120. Update it
accordingly.

Signed-off-by: Gregor Herburger &lt;gregor.herburger@linutronix.de&gt;
Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-6-60832d20ff04@linutronix.de
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
On the -d revision of bcm2712 the uart interrupt is on 120. Update it
accordingly.

Signed-off-by: Gregor Herburger &lt;gregor.herburger@linutronix.de&gt;
Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-6-60832d20ff04@linutronix.de
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: dts: broadcom: bcm2712-d-rpi-5-b: add fixes for pinctrl/pinctrl_aon</title>
<updated>2026-03-16T20:56:16+00:00</updated>
<author>
<name>Gregor Herburger</name>
<email>gregor.herburger@linutronix.de</email>
</author>
<published>2026-02-26T08:55:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=aeb078cebc40d421f61a8f07b0e7919aeb44d751'/>
<id>aeb078cebc40d421f61a8f07b0e7919aeb44d751</id>
<content type='text'>
On the -d revision of the bcm2712 the pinctrl differs from the c0
revision. The driver already supports both and distinguishes the two
with the compatible string.

Update the compatible string and reg length to reflect the different
pinctrl.

Signed-off-by: Gregor Herburger &lt;gregor.herburger@linutronix.de&gt;
Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-5-60832d20ff04@linutronix.de
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
On the -d revision of the bcm2712 the pinctrl differs from the c0
revision. The driver already supports both and distinguishes the two
with the compatible string.

Update the compatible string and reg length to reflect the different
pinctrl.

Signed-off-by: Gregor Herburger &lt;gregor.herburger@linutronix.de&gt;
Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-5-60832d20ff04@linutronix.de
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: dts: broadcom: bcm2712-rpi-5-b: add pinctrl properties for csi i2cs</title>
<updated>2026-03-16T20:55:56+00:00</updated>
<author>
<name>Gregor Herburger</name>
<email>gregor.herburger@linutronix.de</email>
</author>
<published>2026-02-26T08:55:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=783922597a48e1bb8dfea5e196eb080d88e5967a'/>
<id>783922597a48e1bb8dfea5e196eb080d88e5967a</id>
<content type='text'>
Configure the i2c pins for the csi interfaces as i2c.

Signed-off-by: Gregor Herburger &lt;gregor.herburger@linutronix.de&gt;
Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-4-60832d20ff04@linutronix.de
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Configure the i2c pins for the csi interfaces as i2c.

Signed-off-by: Gregor Herburger &lt;gregor.herburger@linutronix.de&gt;
Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-4-60832d20ff04@linutronix.de
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: dts: broadcom: bcm2712: add camera backend node pispbe</title>
<updated>2026-03-16T20:55:46+00:00</updated>
<author>
<name>Gregor Herburger</name>
<email>gregor.herburger@linutronix.de</email>
</author>
<published>2026-02-26T08:55:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=f9b7d552273fd32ec5fd307f48ce40ae6d7ea0c7'/>
<id>f9b7d552273fd32ec5fd307f48ce40ae6d7ea0c7</id>
<content type='text'>
The bcm2712 found in the Raspberry Pi 5 has a PiSP Image Signal
Processor back end image processor.

Add the relevant node to the devicetree.

Signed-off-by: Gregor Herburger &lt;gregor.herburger@linutronix.de&gt;
Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-3-60832d20ff04@linutronix.de
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The bcm2712 found in the Raspberry Pi 5 has a PiSP Image Signal
Processor back end image processor.

Add the relevant node to the devicetree.

Signed-off-by: Gregor Herburger &lt;gregor.herburger@linutronix.de&gt;
Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-3-60832d20ff04@linutronix.de
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: dts: broadcom: rp1: add csi nodes</title>
<updated>2026-03-16T20:55:30+00:00</updated>
<author>
<name>Gregor Herburger</name>
<email>gregor.herburger@linutronix.de</email>
</author>
<published>2026-02-26T08:55:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=cdf38d5997a5cb4ef874602936dfb74a6810f52c'/>
<id>cdf38d5997a5cb4ef874602936dfb74a6810f52c</id>
<content type='text'>
The RaspberryPi 5 has 2 PiSP Camera front end controller on the RP1
chipset.

Add the relevant nodes to the devicetree.

Signed-off-by: Gregor Herburger &lt;gregor.herburger@linutronix.de&gt;
Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-2-60832d20ff04@linutronix.de
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The RaspberryPi 5 has 2 PiSP Camera front end controller on the RP1
chipset.

Add the relevant nodes to the devicetree.

Signed-off-by: Gregor Herburger &lt;gregor.herburger@linutronix.de&gt;
Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-2-60832d20ff04@linutronix.de
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: dts: broadcom: rp1: add i2c controller</title>
<updated>2026-03-16T20:54:38+00:00</updated>
<author>
<name>Gregor Herburger</name>
<email>gregor.herburger@linutronix.de</email>
</author>
<published>2026-02-26T08:55:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=531f5a97394b2dc2606e3d2ee960b783602d7f2e'/>
<id>531f5a97394b2dc2606e3d2ee960b783602d7f2e</id>
<content type='text'>
The RaspberryPi 5 has 7 designware-i2c I2C controller on the RP1
chipset.

Add the relevant nodes to the devicetree.

Signed-off-by: Gregor Herburger &lt;gregor.herburger@linutronix.de&gt;
Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-1-60832d20ff04@linutronix.de
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The RaspberryPi 5 has 7 designware-i2c I2C controller on the RP1
chipset.

Add the relevant nodes to the devicetree.

Signed-off-by: Gregor Herburger &lt;gregor.herburger@linutronix.de&gt;
Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-1-60832d20ff04@linutronix.de
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: dts: broadcom: bcm2712: Add V3D device node</title>
<updated>2026-03-16T19:58:59+00:00</updated>
<author>
<name>Maíra Canal</name>
<email>mcanal@igalia.com</email>
</author>
<published>2026-01-14T12:04:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=80ebada3dbcc811f3f64fc65e49d87857fe9272b'/>
<id>80ebada3dbcc811f3f64fc65e49d87857fe9272b</id>
<content type='text'>
Commits 0ad5bc1ce463 ("drm/v3d: fix up register addresses for V3D 7.x")
and 6fd9487147c4 ("drm/v3d: add brcm,2712-v3d as a compatible V3D device")
added driver support for V3D on BCM2712, but the corresponding device
tree node is still missing.

Add the V3D device tree node to the BCM2712 DTS.

Signed-off-by: Maíra Canal &lt;mcanal@igalia.com&gt;
Reviewed-by: Stefan Wahren &lt;wahrenst@gmx.net&gt;
Link: https://lore.kernel.org/r/20260114120610.82531-1-mcanal@igalia.com
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Commits 0ad5bc1ce463 ("drm/v3d: fix up register addresses for V3D 7.x")
and 6fd9487147c4 ("drm/v3d: add brcm,2712-v3d as a compatible V3D device")
added driver support for V3D on BCM2712, but the corresponding device
tree node is still missing.

Add the V3D device tree node to the BCM2712 DTS.

Signed-off-by: Maíra Canal &lt;mcanal@igalia.com&gt;
Reviewed-by: Stefan Wahren &lt;wahrenst@gmx.net&gt;
Link: https://lore.kernel.org/r/20260114120610.82531-1-mcanal@igalia.com
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc</title>
<updated>2026-02-11T05:11:08+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2026-02-11T05:11:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=6589b3d76db2d6adbf8f2084c303fb24252a0dc6'/>
<id>6589b3d76db2d6adbf8f2084c303fb24252a0dc6</id>
<content type='text'>
Pull SoC devicetree updates from Arnd Bergmann:
 "There are a handful of new SoCs this time, all of these are more or
  less related to chips in a wider family:

   - SpacemiT Key Stone K3 is an 8-core risc-v chip, and the first
     widely available RVA23 implementation. Note that this is entirely
     unrelated with the similarly named Texas Instruments K3 chip family
     that follwed the TI Keystone2 SoC.

   - The Realtek Kent family of SoCs contains three chip models
     rtd1501s, rtd1861b and rtd1920s, and is related to their earlier
     Set-top-box and NAS products such as rtd1619, but is built on newer
     Arm Cortex-A78 cores.

   - The Qualcomm Milos family includes the Snapdragon 7s Gen 3 (SM7635)
     mobile phone SoC built around Armv9 Kryo cores of the Arm
     Cortex-A720 generation. This one is used in the Fairphone Gen 6

   - Qualcomm Kaanapali is a new SoC based around eight high performance
     Oryon CPU cores

   - NXP i.MX8QP and i.MX952 are both feature reduced versions of chips
     we already support, i.e. the i.MX8QM and i.MX952, with fewer CPU
     cores and I/O interfaces.

  As part of a cleanup, a number of SoC specific devicetree files got
  removed because they did not have a single board using the .dtsi files
  and they were never compile tested as a result: Samsung s3c6400, ST
  spear320s, ST stm32mp21xc/stm32mp23xc/stm32mp25xc, Renesas
  r8a779m0/r8a779m2/r8a779m4/r8a779m6/r8a779m7/r8a779m8/r8a779mb/
  r9a07g044c1/r9a07g044l1/r9a07g054l1/r9a09g047e37, and TI
  am3703/am3715. All of these could be restored easily if a new board
  gets merged.

  Broadcom/Cavium/Marvell ThunderX2 gets removed along with its only
  machine, as all remaining users are assumed to be using ACPI based
  firmware.

  A relatively small number of 43 boards get added this time, and almost
  all of them for arm64. Aside from the reference boards for the newly
  added SoCs, this includes:

   - Three server boards use 32-bit ASpeed BMCs

   - One more reference board for 32-bit Microchip LAN9668

   - 64-bit Arm single-board computers based on Amlogic s905y4, CIX
     sky1, NXP ls1028a/imx8mn/imx8mp/imx91/imx93/imx95, Qualcomm
     qcs6490/qrb2210 and Rockchip rk3568/rk3588s

   - Carrier board for SOMs using Intel agilex5, Marvell Armada 7020,
     NXP iMX8QP, Mediatek mt8370/mt8390 and rockchip rk3588

   - Two mobile phones using Snapdragon 845

   - A gaming device and a NAS box, both based on Rockchips rk356x

  On top of the newly added boards and SoCs, there is a lot of
  background activity going into cleanups, in particular towards getting
  a warning-free dtc build, and the usual work on adding support for
  more hardware on the previously added machines"

* tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (757 commits)
  dt-bindings: intel: Add Agilex eMMC support
  arm64: dts: socfpga: agilex: add emmc support
  arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node
  ARM: dts: socfpga: fix dtbs_check warning for fpga-region
  ARM: dts: socfpga: add #address-cells and #size-cells for sram node
  dt-bindings: altera: document syscon as fallback for sys-mgr
  arm64: dts: altera: Use lowercase hex
  dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml
  arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes
  arm64: dts: socfpga: agilex5: add support for modular board
  dt-bindings: intel: Add Agilex5 SoCFPGA modular board
  arm64: dts: socfpga: agilex5: Add dma-coherent property
  arm64: dts: realtek: Add Kent SoC and EVB device trees
  dt-bindings: arm: realtek: Add Kent Soc family compatibles
  ARM: dts: samsung: Drop s3c6400.dtsi
  ARM: dts: nuvoton: Minor whitespace cleanup
  MAINTAINERS: Add Falcon DB
  arm64: dts: a7k: add COM Express boards
  ARM: dts: microchip: Drop usb_a9g20-dab-mmx.dtsi
  arm64: dts: rockchip: Fix rk3588 PCIe range mappings
  ...
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull SoC devicetree updates from Arnd Bergmann:
 "There are a handful of new SoCs this time, all of these are more or
  less related to chips in a wider family:

   - SpacemiT Key Stone K3 is an 8-core risc-v chip, and the first
     widely available RVA23 implementation. Note that this is entirely
     unrelated with the similarly named Texas Instruments K3 chip family
     that follwed the TI Keystone2 SoC.

   - The Realtek Kent family of SoCs contains three chip models
     rtd1501s, rtd1861b and rtd1920s, and is related to their earlier
     Set-top-box and NAS products such as rtd1619, but is built on newer
     Arm Cortex-A78 cores.

   - The Qualcomm Milos family includes the Snapdragon 7s Gen 3 (SM7635)
     mobile phone SoC built around Armv9 Kryo cores of the Arm
     Cortex-A720 generation. This one is used in the Fairphone Gen 6

   - Qualcomm Kaanapali is a new SoC based around eight high performance
     Oryon CPU cores

   - NXP i.MX8QP and i.MX952 are both feature reduced versions of chips
     we already support, i.e. the i.MX8QM and i.MX952, with fewer CPU
     cores and I/O interfaces.

  As part of a cleanup, a number of SoC specific devicetree files got
  removed because they did not have a single board using the .dtsi files
  and they were never compile tested as a result: Samsung s3c6400, ST
  spear320s, ST stm32mp21xc/stm32mp23xc/stm32mp25xc, Renesas
  r8a779m0/r8a779m2/r8a779m4/r8a779m6/r8a779m7/r8a779m8/r8a779mb/
  r9a07g044c1/r9a07g044l1/r9a07g054l1/r9a09g047e37, and TI
  am3703/am3715. All of these could be restored easily if a new board
  gets merged.

  Broadcom/Cavium/Marvell ThunderX2 gets removed along with its only
  machine, as all remaining users are assumed to be using ACPI based
  firmware.

  A relatively small number of 43 boards get added this time, and almost
  all of them for arm64. Aside from the reference boards for the newly
  added SoCs, this includes:

   - Three server boards use 32-bit ASpeed BMCs

   - One more reference board for 32-bit Microchip LAN9668

   - 64-bit Arm single-board computers based on Amlogic s905y4, CIX
     sky1, NXP ls1028a/imx8mn/imx8mp/imx91/imx93/imx95, Qualcomm
     qcs6490/qrb2210 and Rockchip rk3568/rk3588s

   - Carrier board for SOMs using Intel agilex5, Marvell Armada 7020,
     NXP iMX8QP, Mediatek mt8370/mt8390 and rockchip rk3588

   - Two mobile phones using Snapdragon 845

   - A gaming device and a NAS box, both based on Rockchips rk356x

  On top of the newly added boards and SoCs, there is a lot of
  background activity going into cleanups, in particular towards getting
  a warning-free dtc build, and the usual work on adding support for
  more hardware on the previously added machines"

* tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (757 commits)
  dt-bindings: intel: Add Agilex eMMC support
  arm64: dts: socfpga: agilex: add emmc support
  arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node
  ARM: dts: socfpga: fix dtbs_check warning for fpga-region
  ARM: dts: socfpga: add #address-cells and #size-cells for sram node
  dt-bindings: altera: document syscon as fallback for sys-mgr
  arm64: dts: altera: Use lowercase hex
  dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml
  arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes
  arm64: dts: socfpga: agilex5: add support for modular board
  dt-bindings: intel: Add Agilex5 SoCFPGA modular board
  arm64: dts: socfpga: agilex5: Add dma-coherent property
  arm64: dts: realtek: Add Kent SoC and EVB device trees
  dt-bindings: arm: realtek: Add Kent Soc family compatibles
  ARM: dts: samsung: Drop s3c6400.dtsi
  ARM: dts: nuvoton: Minor whitespace cleanup
  MAINTAINERS: Add Falcon DB
  arm64: dts: a7k: add COM Express boards
  ARM: dts: microchip: Drop usb_a9g20-dab-mmx.dtsi
  arm64: dts: rockchip: Fix rk3588 PCIe range mappings
  ...
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: dts: broadcom: bcm4906-netgear-r8000p: Drop unnecessary "ranges" in partition node</title>
<updated>2026-01-16T21:48:58+00:00</updated>
<author>
<name>Rob Herring (Arm)</name>
<email>robh@kernel.org</email>
</author>
<published>2026-01-08T23:15:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=a95e1d848972dd7d5cbabd62921b9b85501d891e'/>
<id>a95e1d848972dd7d5cbabd62921b9b85501d891e</id>
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"ranges" is only valid for MMIO addresses as it is used for translating
addresses to CPU address. Even if a partial translation was supported,
the DT is incorrect here as the nvmem-layout node would also need
"ranges". So drop "ranges" and the associated cell size properties.

Signed-off-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/20260108231558.1422454-2-robh@kernel.org
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
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"ranges" is only valid for MMIO addresses as it is used for translating
addresses to CPU address. Even if a partial translation was supported,
the DT is incorrect here as the nvmem-layout node would also need
"ranges". So drop "ranges" and the associated cell size properties.

Signed-off-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/20260108231558.1422454-2-robh@kernel.org
Signed-off-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
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