linux.git/arch/arm/net, branch v4.19

ARM: net: bpf: improve 64-bit ALU implementation

2018-07-13T13:26:42+00:00

Improbe the 64-bit ALU implementation from:

  movw    r8, #65532
  movt    r8, #65535
  movw    r9, #65535
  movt    r9, #65535
  ldr     r7, [fp, #-44]
  adds    r7, r7, r8
  str     r7, [fp, #-44]
  ldr     r7, [fp, #-40]
  adc     r7, r7, r9
  str     r7, [fp, #-40]

to:

  movw    r8, #65532
  movt    r8, #65535
  movw    r9, #65535
  movt    r9, #65535
  ldrd    r6, [fp, #-44]
  adds    r6, r6, r8
  adc     r7, r7, r9
  strd    r6, [fp, #-44]

Signed-off-by: Russell King 
Signed-off-by: Daniel Borkmann

ARM: net: bpf: improve 64-bit store implementation

2018-07-13T13:26:42+00:00

Improve the 64-bit store implementation from:

  ldr     r6, [fp, #-8]
  str     r8, [r6]
  ldr     r6, [fp, #-8]
  mov     r7, #4
  add     r7, r6, r7
  str     r9, [r7]

to:

  ldr     r6, [fp, #-8]
  str     r8, [r6]
  str     r9, [r6, #4]

We leave the store as two separate STR instructions rather than using
STRD as the store may not be aligned, and STR can handle misalignment.

Signed-off-by: Russell King 
Signed-off-by: Daniel Borkmann

ARM: net: bpf: improve 64-bit sign-extended immediate load

2018-07-13T13:26:41+00:00

Improve the 64-bit sign-extended immediate from:

  mov     r6, #1
  str     r6, [fp, #-52]  ; 0xffffffcc
  mov     r6, #0
  str     r6, [fp, #-48]  ; 0xffffffd0

to:

  mov     r6, #1
  mov     r7, #0
  strd    r6, [fp, #-52]  ; 0xffffffcc

Signed-off-by: Russell King 
Signed-off-by: Daniel Borkmann

ARM: net: bpf: improve 64-bit load immediate implementation

2018-07-13T13:26:41+00:00

Rather than writing each 32-bit half of the 64-bit immediate value
separately when the register is on the stack:

  movw    r6, #45056      ; 0xb000
  movt    r6, #60979      ; 0xee33
  str     r6, [fp, #-44]  ; 0xffffffd4
  mov     r6, #0
  str     r6, [fp, #-40]  ; 0xffffffd8

arrange to use the double-word store when available instead:

  movw    r6, #45056      ; 0xb000
  movt    r6, #60979      ; 0xee33
  mov     r7, #0
  strd    r6, [fp, #-44]  ; 0xffffffd4

Signed-off-by: Russell King 
Signed-off-by: Daniel Borkmann

ARM: net: bpf: use double-word load/stores where available

2018-07-12T18:45:23+00:00

Use double-word load and stores where support for this instruction is
supported by the CPU architecture.

Signed-off-by: Russell King 
Signed-off-by: Daniel Borkmann

ARM: net: bpf: always use odd/even register pair

2018-07-12T18:45:23+00:00

Always use an odd/even register pair for our 64-bit registers, so that
we're able to use the double-word load/store instructions in the future.

Signed-off-by: Russell King 
Signed-off-by: Daniel Borkmann

ARM: net: bpf: avoid reloading 'array'

2018-07-12T18:45:23+00:00

Rearranging the order of the initial tail call code a little allows is
to avoid reloading the 'array' pointer.

Signed-off-by: Russell King 
Signed-off-by: Daniel Borkmann

ARM: net: bpf: avoid reloading 'index'

2018-07-12T18:45:23+00:00

Avoid reloading 'index' after we have validated it - it remains in
tmp2[1] up to the point that we begin the code to index the pointer
array, so with a little rearrangement of the registers, we can use
the already loaded value.

Signed-off-by: Russell King 
Signed-off-by: Daniel Borkmann

ARM: net: bpf: use ldr instructions with shifted rm register

2018-07-12T18:45:23+00:00

Rather than pre-shifting the rm register for the ldr in the tail call,
shift it in the load instruction.  This eliminates one unnecessary
instruction.

Signed-off-by: Russell King 
Signed-off-by: Daniel Borkmann

ARM: net: bpf: use immediate forms of instructions where possible

2018-07-12T18:45:23+00:00

Rather than moving constants to a register and then using them in a
subsequent instruction, use them directly in the desired instruction
cutting out the "middle" register.  This removes two instructions from
the tail call code path.

Signed-off-by: Russell King 
Signed-off-by: Daniel Borkmann