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<title>linux.git/arch/arm/kernel/setup.c, branch v2.6.37</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>Merge branches 'at91', 'dcache', 'ftrace', 'hwbpt', 'misc', 'mmci', 's3c', 'st-ux' and 'unwind' into devel</title>
<updated>2010-10-18T21:34:25+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2010-10-18T21:34:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=23beab76b490172a9ff3d52843e4d27a35b2a4c6'/>
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<pre>
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</entry>
<entry>
<title>ARM: vmlinux.lds: Refer to start of .data using _sdata rather than _data</title>
<updated>2010-10-08T09:02:24+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2010-10-01T13:12:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=842eab40b6920819fff5caeefdb709f07d3f8e23'/>
<id>842eab40b6920819fff5caeefdb709f07d3f8e23</id>
<content type='text'>
Use _sdata as the start of the data section, rather than _data.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
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<pre>
Use _sdata as the start of the data section, rather than _data.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
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</content>
</entry>
<entry>
<title>ARM: 6431/1: fix isb regression on CPU &lt; v7</title>
<updated>2010-10-08T08:59:36+00:00</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@stericsson.com</email>
</author>
<published>2010-10-06T10:07:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=5fb31a96e1e0078f1e82736ccd72a61ecabe6a4f'/>
<id>5fb31a96e1e0078f1e82736ccd72a61ecabe6a4f</id>
<content type='text'>
The kernel does not compile for my ARM926EJ-S system U300 due to
the isb instruction inserted in generic assember statement from
commit 8925ec4c530094b878e7e28a1fd78e7122afd973, "ARM: 6385/1:
setup: detect aliasing I-cache when D-cache is non-aliasing"
hey the isb is only available when assembling for v7 so let's
use the generic isb() macro from setup.h instead.

Acked-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@stericsson.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
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The kernel does not compile for my ARM926EJ-S system U300 due to
the isb instruction inserted in generic assember statement from
commit 8925ec4c530094b878e7e28a1fd78e7122afd973, "ARM: 6385/1:
setup: detect aliasing I-cache when D-cache is non-aliasing"
hey the isb is only available when assembling for v7 so let's
use the generic isb() macro from setup.h instead.

Acked-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@stericsson.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
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</content>
</entry>
<entry>
<title>ARM: 6385/1: setup: detect aliasing I-cache when D-cache is non-aliasing</title>
<updated>2010-10-04T19:57:09+00:00</updated>
<author>
<name>Will Deacon</name>
<email>will.deacon@arm.com</email>
</author>
<published>2010-09-13T15:18:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=8925ec4c530094b878e7e28a1fd78e7122afd973'/>
<id>8925ec4c530094b878e7e28a1fd78e7122afd973</id>
<content type='text'>
Currently, the Kernel assumes that if a CPU has a non-aliasing D-cache
then the I-cache is also non-aliasing. This may not be true on ARM cores
from v6 onwards, which may have aliasing I-caches but non-aliasing
D-caches.

This patch adds a cpu_has_aliasing_icache function, which is called from
cacheid_init and adds CACHEID_VIPT_I_ALIASING to the cacheid when
appropriate. A utility macro, icache_is_vipt_aliasing(), is also
provided.

Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
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Currently, the Kernel assumes that if a CPU has a non-aliasing D-cache
then the I-cache is also non-aliasing. This may not be true on ARM cores
from v6 onwards, which may have aliasing I-caches but non-aliasing
D-caches.

This patch adds a cpu_has_aliasing_icache function, which is called from
cacheid_init and adds CACHEID_VIPT_I_ALIASING to the cacheid when
appropriate. A utility macro, icache_is_vipt_aliasing(), is also
provided.

Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
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</content>
</entry>
<entry>
<title>ARM: Allow SMP kernels to boot on UP systems</title>
<updated>2010-10-04T19:23:36+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2010-09-04T09:47:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=f00ec48fadf5e37e7889f14cff900aa70d18b644'/>
<id>f00ec48fadf5e37e7889f14cff900aa70d18b644</id>
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UP systems do not implement all the instructions that SMP systems have,
so in order to boot a SMP kernel on a UP system, we need to rewrite
parts of the kernel.

Do this using an 'alternatives' scheme, where the kernel code and data
is modified prior to initialization to replace the SMP instructions,
thereby rendering the problematical code ineffectual.  We use the linker
to generate a list of 32-bit word locations and their replacement values,
and run through these replacements when we detect a UP system.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
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<pre>
UP systems do not implement all the instructions that SMP systems have,
so in order to boot a SMP kernel on a UP system, we need to rewrite
parts of the kernel.

Do this using an 'alternatives' scheme, where the kernel code and data
is modified prior to initialization to replace the SMP instructions,
thereby rendering the problematical code ineffectual.  We use the linker
to generate a list of 32-bit word locations and their replacement values,
and run through these replacements when we detect a UP system.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'devel-stable' into devel</title>
<updated>2010-07-31T13:20:16+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2010-07-31T13:20:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=7b70c4275f28702b76b273c8534c38f8313812e9'/>
<id>7b70c4275f28702b76b273c8534c38f8313812e9</id>
<content type='text'>
Conflicts:
	arch/arm/kernel/entry-armv.S
	arch/arm/kernel/setup.c
	arch/arm/mm/init.c
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<pre>
Conflicts:
	arch/arm/kernel/entry-armv.S
	arch/arm/kernel/setup.c
	arch/arm/mm/init.c
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branches 'at91', 'ep93xx', 'kexec', 'iop', 'lmb', 'nomadik', 'nuc', 'pl', 'spear' and 'versatile' into devel</title>
<updated>2010-07-31T13:19:35+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2010-07-31T13:19:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=b31fc7af78e17b0203e1cd5a195c590e8adeae0d'/>
<id>b31fc7af78e17b0203e1cd5a195c590e8adeae0d</id>
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<pre>
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</content>
</entry>
<entry>
<title>ARM: Convert platform reservations to use LMB rather than bootmem</title>
<updated>2010-07-27T07:48:23+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2010-05-22T18:47:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=8d717a52d1b0959128be5134dd12608e8e4f2115'/>
<id>8d717a52d1b0959128be5134dd12608e8e4f2115</id>
<content type='text'>
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
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<pre>
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: initial LMB trial</title>
<updated>2010-07-27T07:48:22+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2010-07-09T15:27:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=2778f62056ada442414392d7ccd41188bb631619'/>
<id>2778f62056ada442414392d7ccd41188bb631619</id>
<content type='text'>
Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
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<pre>
Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: Remove DISCONTIGMEM support</title>
<updated>2010-07-16T09:57:35+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2010-05-07T16:40:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=be370302742ff9948f2a42b15cb2ba174d97b930'/>
<id>be370302742ff9948f2a42b15cb2ba174d97b930</id>
<content type='text'>
Everything should now be using sparsemem rather than discontigmem, so
remove the code supporting discontigmem from ARM.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
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<pre>
Everything should now be using sparsemem rather than discontigmem, so
remove the code supporting discontigmem from ARM.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
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