linux.git/arch/arm/kernel/perf_event_xscale.c, branch v3.2

ARM: perf: remove cpu-related misnomers

2011-08-31T09:50:12+00:00

Currently struct cpu_hw_events stores data on events running on a
PMU associated with a CPU. As this data is general enough to be used
for system PMUs, this name is a misnomer, and may cause confusion when
it is used for system PMUs.

Additionally, 'armpmu' is commonly used as a parameter name for an
instance of struct arm_pmu. The name is also used for a global instance
which represents the CPU's PMU.

As cpu_hw_events is now not tied to CPU PMUs, it is renamed to
pmu_hw_events, with instances of it renamed similarly. As the global
'armpmu' is CPU-specfic, it is renamed to cpu_pmu. This should make it
clearer which code is generic, and which is coupled with the CPU.

Signed-off-by: Mark Rutland 
Reviewed-by: Will Deacon 
Reviewed-by: Jamie Iles 
Reviewed-by: Ashwin Chaugule 
Signed-off-by: Will Deacon

ARM: perf: refactor event mapping

2011-08-31T09:50:09+00:00

Currently mapping an event type to a hardware configuration value
depends on the data being pointed to from struct arm_pmu. These fields
(cache_map, event_map, raw_event_mask) are currently specific to CPU
PMUs, and do not serve the general case well.

This patch replaces the event map pointers on struct arm_pmu with a new
'map_event' function pointer. Small shim functions are used to reuse
the existing common code.

Signed-off-by: Mark Rutland 
Reviewed-by: Will Deacon 
Reviewed-by: Jamie Iles 
Reviewed-by: Ashwin Chaugule 
Signed-off-by: Will Deacon

ARM: perf: lock PMU registers per-CPU

2011-08-31T09:50:07+00:00

Currently, a single lock serialises access to CPU PMU registers. This
global locking is unnecessary as PMU registers are local to the CPU
they monitor.

This patch replaces the global lock with a per-CPU lock. As the lock is
in struct cpu_hw_events, PMUs providing a single cpu_hw_events instance
can be locked globally.

Signed-off-by: Mark Rutland 
Reviewed-by: Will Deacon 
Reviewed-by: Jamie Iles 
Reviewed-by: Ashwin Chaugule 
Signed-off-by: Will Deacon

ARM: perf: remove active_mask

2011-08-31T09:50:02+00:00

Currently, pmu_hw_events::active_mask is used to keep track of which
events are active in hardware. As we can stop counters and their
interrupts, this is unnecessary.

Signed-off-by: Mark Rutland 
Reviewed-by: Will Deacon 
Reviewed-by: Jamie Iles 
Reviewed-by: Ashwin Chaugule 
Signed-off-by: Will Deacon

ARM: perf: index Xscale and ARMv6 event counters starting from zero

2011-08-31T09:18:00+00:00

Now that the ARMv7 PMU backend indexes event counters from zero, follow
suit and do the same for ARMv6 and Xscale.

Acked-by: Jamie Iles 
Reviewed-by: Jean Pihet 
Signed-off-by: Mark Rutland 
Signed-off-by: Will Deacon

ARM: perf: de-const struct arm_pmu

2011-08-31T09:16:58+00:00

This patch removes const qualifiers from instances of struct arm_pmu,
and functions initialising them, in preparation for generalising
arm_pmu usage to system (AKA uncore) PMUs.

This will allow for dynamically modifiable structures (locks,
struct pmu) to be added as members of struct arm_pmu.

Acked-by: Jamie Iles 
Reviewed-by: Jean Pihet 
Signed-off-by: Mark Rutland 
Signed-off-by: Will Deacon

perf, arch: Add generic NODE cache events

2011-07-01T09:06:38+00:00

Add a NODE level to the generic cache events which is used to measure
local vs remote memory accesses. Like all other cache events, an
ACCESS is HIT+MISS, if there is no way to distinguish between reads
and writes do reads only etc..

The below needs filling out for !x86 (which I filled out with
unsupported events).

I'm fairly sure ARM can leave it like that since it doesn't strike me as
an architecture that even has NUMA support. SH might have something since
it does appear to have some NUMA bits.

Sparc64, PowerPC and MIPS certainly want a good look there since they
clearly are NUMA capable.

Signed-off-by: Peter Zijlstra 
Cc: David Miller 
Cc: Anton Blanchard 
Cc: David Daney 
Cc: Deng-Cheng Zhu 
Cc: Paul Mundt 
Cc: Will Deacon 
Cc: Robert Richter 
Cc: Stephane Eranian 
Link: http://lkml.kernel.org/r/1303508226.4865.8.camel@laptop
Signed-off-by: Ingo Molnar

perf: Remove the nmi parameter from the swevent and overflow interface

2011-07-01T09:06:35+00:00

The nmi parameter indicated if we could do wakeups from the current
context, if not, we would set some state and self-IPI and let the
resulting interrupt do the wakeup.

For the various event classes:

  - hardware: nmi=0; PMI is in fact an NMI or we run irq_work_run from
    the PMI-tail (ARM etc.)
  - tracepoint: nmi=0; since tracepoint could be from NMI context.
  - software: nmi=[0,1]; some, like the schedule thing cannot
    perform wakeups, and hence need 0.

As one can see, there is very little nmi=1 usage, and the down-side of
not using it is that on some platforms some software events can have a
jiffy delay in wakeup (when arch_irq_work_raise isn't implemented).

The up-side however is that we can remove the nmi parameter and save a
bunch of conditionals in fast paths.

Signed-off-by: Peter Zijlstra 
Cc: Michael Cree 
Cc: Will Deacon 
Cc: Deng-Cheng Zhu 
Cc: Anton Blanchard 
Cc: Eric B Munson 
Cc: Heiko Carstens 
Cc: Paul Mundt 
Cc: David S. Miller 
Cc: Frederic Weisbecker 
Cc: Jason Wessel 
Cc: Don Zickus 
Link: http://lkml.kernel.org/n/tip-agjev8eu666tvknpb3iaj0fg@git.kernel.org
Signed-off-by: Ingo Molnar

ARM: 6835/1: perf: ensure overflows aren't missed due to IRQ latency

2011-03-26T10:06:09+00:00

If a counter overflows during a perf stat profiling run it may overtake
the last known value of the counter:

    0        prev     new                0xffffffff
    |----------|-------|----------------------|

In this case, the number of events that have occurred is
(0xffffffff - prev) + new. Unfortunately, the event update code will
not realise an overflow has occurred and will instead report the event
delta as (new - prev) which may be considerably smaller than the real
count.

This patch adds an extra argument to armpmu_event_update which indicates
whether or not an overflow has occurred. If an overflow has occurred
then we use the maximum period of the counter to calculate the elapsed
events.

Acked-by: Jamie Iles 
Reported-by: Ashwin Chaugule 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King

ARM: 6521/1: perf: use raw_spinlock_t for pmu_lock

2010-12-04T11:18:08+00:00

For kernels built with PREEMPT_RT, critical sections protected
by standard spinlocks are preemptible. This is not acceptable
on perf as (a) we may be scheduled onto a different CPU whilst
reading/writing banked PMU registers and (b) the latency when
reading the PMU registers becomes unpredictable.

This patch upgrades the pmu_lock spinlock to a raw_spinlock
instead.

Reported-by: Jamie Iles 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King